VLSI-SoC C

61 papers

YearTitle / Authors
2007A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD.
YuQing Yang, Terry Sculley, Jacob Abraham
2007A Flexible Design Flow for a Low Power RFID Tag.
José Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo A. Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler
2007A VHDL based approach for fast and accurate energy consumption estimations.
César A. M. Marcon, Sergio Johann Filho, Fabiano Hessel
2007A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.
M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
2007A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.
Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay
2007A high-driving class-AB buffer amplifier with a new pseudo source follower.
Chih-Wen Lu, Yen-Chih Shen, Meng-Lieh Sheu
2007A low-power CAM using a 12-transistor design cell.
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
2007A low-power deblocking filter architecture for H.264 advanced video coding.
Jaemoon Kim, Sangkwon Na, Chong-Min Kyung
2007A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci
2007A new analytical approach of the impact of jitter on continuous time delta sigma converters.
Julien Goulier, Eric André, Marc Renaudin
2007A software-supported methodology for designing high-performance 3D FPGA architectures.
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris
2007AC-coupling strategy for high-speed transceivers of 10Gbps and beyond.
Yikui Dong, Steve Howard, Freeman Zhong, Scott Lowrie, Ken Paradis, Jan Kolnik, Jeff Burleson
2007An HDTV H.264 deblocking filter in FPGA with RGB video output.
Vagner S. Rosa, Altamiro Amadeu Susin, Sergio Bampi
2007An adaptive genetic algorithm for dynamically reconfigurable modules allocation.
Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto
2007An analog programmable multi-dimensional radial basis function based classifier.
Sheng-Yu Peng, Paul E. Hasler, David V. Anderson
2007An efficient H.264 intra frame coder system design.
Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin
2007An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor.
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour
2007Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.
Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar
2007Co-synthesis of custom on-chip bus and memory for MPSoC architectures.
Sujan Pandey, Christian Genz, Rolf Drechsler
2007Computing and design for software and silicon manufacturing.
Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi
2007Dynamic gates with hysteresis and configurable noise tolerance.
Krishna Santhanam, Kenneth S. Stevens
2007Efficient DSP algorithm development for FPGA and ASIC technologies.
Shiv Balakrishnan, Chris Eddington
2007Efficient timing closure with a transistor level design flow.
Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis
2007Estimating design time for system circuits.
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau
2007Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack.
Jean Carlo Hamerski, Everton Reckziegel, Fernanda Lima Kastensmidt
2007Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.
Jungsoo Kim, Kyungsu Kang, Heejun Shim, Woong Hwangbo, Chong-Min Kyung
2007First order quasi-static SOI MOSFET channel capacitance model.
Sameer Sharma, L. G. Johnson
2007Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 mum CMO S.
Run Chen, Liyuan Liu, Dongmei Li, Zhihua Wang
2007Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators.
Hua Tang
2007High speed SOC design for blowfish cryptographic algorithm.
Brian Cody, Justin Madigan, Spencer MacDonald, Kenneth W. Hsu
2007Hybrid multiplierless FIR filter architecture based on NEDA.
Jose Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce, Magdy A. Bayoumi
2007IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007
2007Impact of hardware emulation on the verification quality improvement.
Youssef Serrestou, Vincent Beroulle, Chantal Robach
2007Impact of task migration in NoC-based MPSoCs for soft real-time applications.
Eduardo Wenzel Brião, Daniel Barcelos, Fabio Wronski, Flávio Rech Wagner
2007Implementing cellular automata modeled applications on network-on-chip platforms.
Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris
2007Improvement of dual rail logic as a countermeasure against DPA.
Alin Razafindraibe, Michel Robert, Philippe Maurine
2007Incremental placement for structured ASICs using the transportation problem.
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007Low power on-chip thermal sensors based on wires.
Basab Datta, Wayne P. Burleson
2007Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.
Vyas Krishnan, Srinivas Katkoori
2007Neuromorphic building blocks for adaptable cortical feature maps.
C. M. Markan, Priti Gupta
2007New parallel programming techniques for hardware design.
Satnam Singh
2007New tool support and architectures in adaptive reconfigurable computing.
Jürgen Becker, Adam Donlin, Michael Hübner
2007Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.
Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis
2007Optimum IR drop models for estimation of metal resource requirements for power distribution network.
Rishi Bhooshan, Bindu P. Rao
2007Parallelized radix-2 scalable Montgomery multiplier.
Nan Jiang, David Money Harris
2007Parametric structure-preserving model order reduction.
Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira
2007Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.
Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri
2007Power optimization for conditional task graphs in DVS enabled multiprocessor systems.
Parth Malani, Prakash Mukre, Qinru Qiu
2007Qualification of behavioral level design validation for AMS & RF SoCs.
Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro
2007Rate-based scheduling policy for QoS flows in networks on chip.
Aline Mello, Ney Laert Vilar Calazans
2007ReCPU: A parallel and pipelined architecture for regular expression matching.
Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio
2007Regression based circuit matrix models for accurate performance estimation of analog circuits.
Almitra Pradhan, Ranga Vemuri
2007SWORD: A SAT like prover using word level information.
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007Simulation of hybrid computer architectures: simulators, methodologies and recommendations.
Pranav Vaidya, Jaehwan John Lee
2007Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Gilson I. Wirth, Ralf Brederlow, Christian Pacha
2007Test data compression and TAM design.
Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
2007The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.
Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
2007Transistor level automatic layout generator for non-complementary CMOS cells.
Adriel Ziesemer, Cristiano Lazzari
2007Transparent acceleration of data dependent instructions for general purpose processors.
Antonio Carlos Schneider Beck, Luigi Carro
2007Use of gray decoding for implementation of symmetric functions.
Osnat Keren, Ilya Levin, Radomir S. Stankovic
2007VLSI models of network-on-chip interconnect.
Dimitrios N. Serpanos, Wayne H. Wolf