VLSI-SoC C

76 papers

YearTitle / Authors
2006A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.
Shan Jiang, Manh Anh Do, Kiat Seng Yeo
2006A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD.
Yue-Fang Kuo, Ro-Min Weng, Chun-Yu Liu
2006A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.
Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai
2006A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli
2006A Fast SAT Solver Strategy Based on Negated Clauses.
Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
2006A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.
Sinan Yalcin, Ilker Hamzaoglu
2006A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.
Sanghun Lee, Chanho Lee
2006A New Phase Noise Model for TSPC based divider.
Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo
2006A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
2006A Predictable Communication Scheme for Embedded Multiprocessor Systems.
Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
2006A VHDL Generation Tool for Optimized Parallel FIR Filters.
Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi
2006A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.
Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini
2006A low power high performance CMOS voltage-mode quaternary full adder.
Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro
2006An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.
Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2006An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane
2006An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures.
Hsin-Chou Chi, Chia-Ming Wu
2006An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them.
A. Domman
2006Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.
Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi
2006Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.
Sam Kavusi, Kunal Ghosh, Abbas El Gamal
2006Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging.
Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
2006BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.
Malav Shah, Dipankar Nagchoudhuri
2006CAT platform for analogue and mixed-signal test evaluation and optimization.
Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
2006Can Asynchronous Techniques Help the SoC Designer?
Alain J. Martin
2006Circuit and Device Technologies for CMOS functional Image Sensors.
Shoji Kawahito
2006Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen
2006Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2006Design challenges for the 45 nm node and below.
Jean-Pierre Schoellkopf
2006Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.
Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez
2006Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems.
Ravindra V. Kshirsagar, Rajendra M. Patrikar
2006Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006Detecting DNA by field effect transistor arrays.
Ulrich Bockelmann
2006Directed Convergence Heuristic: A fast & novel approach to Steiner Tree Construction.
Shampa Chakraverty, Arvind Batra, Aman Rathi
2006EXOR Projected Sum of Products.
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2006Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
2006Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
Sujan Pandey, Tudor Murgan, Manfred Glesner
2006Energy-Effcient Scheduling for Autonomous Mobile Robots.
Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu
2006Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.
Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
2006Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.
Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
2006High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor.
Senthamaraikannan Raghunath, Syed Mahfuzul Aziz
2006High-Throughput Montgomery Modular Multiplication.
Ramachandruni Venkata Kamala, M. B. Srinivas
2006Human++: Emerging Technology for Body Area Networks.
Bert Gyselinckx, Ruud J. M. Vullers, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov
2006IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006
2006Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
2006Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.
Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes
2006Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.
Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, Augusto Nascetti, Davide Caputo, Giampiero de Cesare
2006Introduction to panel discussion Probabilistic & statistical design - the wave of the future.
Shekhar Borkar
2006MDCT IP Core Generator with Architectural Model Simulation.
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
2006Main Memory Energy Optimization for Multi-Task Applications.
Hanene Ben Fradj, Cécile Belleudy, Michel Auguin
2006Modelling Heterogeneous Interactions in SoC Verification.
Justin Xu, Cheng-Chew Lim
2006Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
2006On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.
Chin-Cheng Kuo, Chien-Nan Jimmy Liu
2006On-Line Test Vector Generation from Temporal Constraints Written in PSL.
Yann Oddos, Katell Morin-Allory, Dominique Borrione
2006Organic Computing at the System on Chip Level.
Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
2006Oversampled Time Estimation Techniques for Precision Photonic Detectors.
Robert K. Henderson, Bruce Rae, David Renshaw, Edoardo Charbon
2006PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.
Shih-Chieh Wu, Chun-Yao Wang
2006Probabilistic CMOS Technology: A Survey and Future Directions.
Bilge Saglam Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem
2006Pseudo Floating-Gate Inverter with Feedback Control.
Yngvar Berg, Omid Mirmotahari, Snorre Aunet
2006Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
2006Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei
2006SOC Debug Challenges and Tools.
K. Schultz, Ketan Paranjape
2006Security evaluation of dual rail logic against DPA attacks.
Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
2006Signal Coverage Computation in Formal Verification.
Hamid Shojaei, Mohammad Sayyaran
2006Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner
2006Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.
Se Hun Kim, Vincent John Mooney
2006Soft Error Resilient System Design through Error Correction.
Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
2006State-holding in Look-Up Tables: application to asynchronous logic.
Laurent Fesquet, Bertrand Folco, Mathieu Steiner, Marc Renaudin
2006Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
2006Study of a BIST Technique for CMOS Active Pixel Sensors.
Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur
2006System-level Dynamic Power Management Techniques for Communication Intensive Devices.
Rodrigo M. Passos, José Augusto Miranda Nacif, Raquel A. F. Mini, Antonio Alfredo Ferreira Loureiro, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.
2006Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.
Sujan Pandey, Nurten Utlu, Manfred Glesner
2006Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2006Technical Documentation of Software and Hardware in Embedded Systems.
Beate Muranko, Rolf Drechsler
2006The Demand and Practical Approach for 100x Test Compression.
Ron Press, Jay Jahangiri
2006The system is really in the SoC : new investment opportunities.
Jacques Benkowski
2006Variation-Aware, Library Compatible Delay Modeling Strategy.
Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira