| 2023 | Extending Memory Compatibility with Yosys Front-End in VTR Flow. Alireza Azadi, Amir Arjomand, Kenneth B. Kent |
| 2023 | Fast Compiler Optimization Flag Selection. Melih Peker, Ozcan Ozturk |
| 2023 | Fast and Accurate Virtual Prototyping of an NPU with Analytical Memory Modeling. Choonghoon Park, Hyunsu Moh, Jimin Lee, Changjae Yi, Soonhoi Ha |
| 2023 | HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. Fearghal Morgan, John Patrick Byrne, Abishek Bupathi, Roshan George, Muhammad Adnan Elahi, Frank Callaly, Sean Kelly, Declan O'Loughlin |
| 2023 | MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping. Tobias Strauch |
| 2023 | Polynomial Formal Verification exploiting Constant Cutwidth. Mohamed A. Nadeem, Jan Kleinekathöfer, Rolf Drechsler |
| 2023 | Proceedings of the 34th International Workshop on Rapid System Prototyping, RSP 2023, Hamburg, Germany, 21 September 2023 |
| 2023 | ReDaML: A Modeling Language for DO-178C High-Level Requirements in Airspace Systems. Henrique Amaral Misson, Rim Zrelli, Maroua Ben Attia, Felipe Gohring de Magalhaes, Gabriela Nicolescu |
| 2023 | Secured-by-design systems-on-chip: a MBSE Approach. Raphaële Milan, Loïc Lagadec, Théotime Bollengier, Lilian Bossuet, Ciprian Teodorov |
| 2023 | Security assessment of a commercial router using physical access: a case study. Colin Stephenne, Felipe Gohring de Magalhaes, Frédéric Cuppens, Jean-Yves Ouattara, Militza Jean, Jose Fernandez, Gabriela Nicolescu |
| 2023 | SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems. Felipe G. Magalhaes, Mahdi Nikdast, Gabriela Nicolescu |
| 2023 | The Impact of Heterogeneous Logic on Adders and Multipliers in VTR. Navid Jafarof, Kenneth B. Kent |