| 2021 | An FPGA-based Emulation Platform for Edge Computing Node Design Exploration. Theo Soriano, David Novo, Pascal Benoit |
| 2021 | Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform. Nils Büscher, Daniel Gis, Johann-Peter Wolff, Christian Haubelt |
| 2021 | FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural Networks. Soobeom Kim, Seunghwan Cho, Eunhyeok Park, Sungjoo Yoo |
| 2021 | Heterogeneous Logic Implementation for Adders in VTR. Harpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent |
| 2021 | HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks. Felipe Göhring de Magalhães, Mahdi Nikdast, Fabiano Hessel, Odile Liboiron-Ladouceur, Gabriela Nicolescu |
| 2021 | IEEE International Workshop on Rapid System Prototyping, RSP 2021, Paris, France, October 14, 2021 |
| 2021 | Implementing Rowhammer Memory Corruption in the gem5 Simulator. Loïc France, Florent Bruguier, Maria Mushtaq, David Novo, Pascal Benoit |
| 2021 | Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator. Kevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli |
| 2021 | Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. Bruno Ferres, Olivier Muller, Frédéric Rousseau |
| 2021 | Prototyping FPGA through overlays. Théotime Bollengier, Loïc Lagadec, Ciprian Teodorov |
| 2021 | Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation. Kevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max E. Kramer, Clemens Reichmann |