| 2020 | (System)Verilog to Chisel Translation for Faster Hardware Design. Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot |
| 2020 | A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management. Erwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles |
| 2020 | Advanced Debugging Architecture for Smart Inertial Sensors using Sensor-in-the-Loop. Daniel Gis, Nils Büscher, Christian Haubelt |
| 2020 | Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin II. Seyed Alireza Damghani, Jean-Philippe Legault, Kenneth B. Kent |
| 2020 | FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. Jérémy Nadal, Amer Baghdadi |
| 2020 | Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV. Erwan Moréac, El Mehdi Abdali, François Berry, Dominique Heller, Jean-Philippe Diguet |
| 2020 | International Workshop on Rapid System Prototyping, RSP 2020, Hamburg, Germany, September 24-25, 2020 |
| 2020 | MPSoC Fast Prototyping of a Reconfigurable DU Downlink Transmission Chain for 5G New Radio. José D. Domingues, Fábio D. L. Coutinho, Pedro M. C. Marques, Samuel Santos Pereira, Hugerles S. Silva, Arnaldo S. R. Oliveira |
| 2020 | Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster. Chen Wu, Virginie Fresse, Benoît Suffran, Hubert Konik |
| 2020 | NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks. Xuzhi Zhang, Narendra Prabhu, Russell Tessier |