| 2017 | An analysis of random cache effects on real-time multi-core scheduling algorithms. Imane Hafnaoui, Chao Chen, Rabeh Ayari, Gabriela Nicolescu, Giovanni Beltrame |
| 2017 | Binary synthesis implementing external interrupt handler as independent module. Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama |
| 2017 | Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. Michael Witterauf, Frank Hannig, Jürgen Teich |
| 2017 | Energy-efficient and robust middleware prototyping for smart mobile computing. Saideep Tiku, Sudeep Pasricha |
| 2017 | Executable dataflow benchmark generation technique for multi-core embedded systems. Jeonggyu Jang, Hoeseok Yang |
| 2017 | GeCo: classification restricted Boltzmann machine hardware for on-chip learning. Wooseok Yi, Junki Park, Jae-Joon Kim |
| 2017 | International Symposium on Rapid System Prototyping, RSP 2017, Shortening the Path from Specification to Prototype, October 19-20, 2017, Seoul, South Korea. Sungjoo Yoo, Fabiano Hessel, Frédéric Rousseau, Kenneth B. Kent, Kyoungwoo Lee |
| 2017 | One-instruction set computer-based multicore processors for energy-efficient streaming data processing. Minato Yokota, Kaoru Saso, Yuko Hara-Azumi |
| 2017 | PoIiCym: rapid prototyping of resource management policies for HMPs. Tiago Mück, Bryan Donyanavard, Nikil D. Dutt |
| 2017 | Prototyping dynamic task migration on heterogeneous reconfigurable systems. Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau |
| 2017 | Rapid prototyping of IoT applications with Esperanto compiler. Gyeongmin Lee, Seonyeong Heo, Bongjun Kim, Jong Kim, Hanjun Kim |
| 2017 | Simulation-based circuit-activity estimation for FPGAs containing hard blocks. Sean Seeley, Vidya Sankaranaryanan, Zack Deveau, Panagiotis Patros, Kenneth B. Kent |
| 2017 | Software platform dedicated for in-memory computing circuit evaluation. Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noël |
| 2017 | Speculative execution in distributed controllers for high-level synthesis. Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano |
| 2017 | The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann |
| 2017 | Time synchronization services for low-cost fog computing applications. Péter Völgyesi, Abhishek Dubey, Timothy Krentz, István Madari, Mary Metelko, Gabor Karsai |