MICRO A*

29 papers

YearTitle / Authors
1998A Bandwidth-efficient Architecture for Media Processing.
Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens
1998A Dynamic Multithreading Processor.
Haitham Akkary, Michael A. Driscoll
1998A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification.
Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
1998Analyzing the Working Set Characteristics of Branch Execution.
Sangwook P. Kim, Gary S. Tyson
1998Better Global Scheduling Using Path Profiles.
Cliff Young, Michael D. Smith
1998Code Compression Based on Operand Factorization.
Guido Araujo, Paulo Centoducatte, Mario Lúcio Côrtes, Ricardo Pannain
1998Compiler-Directed Early Load-Address Generation.
Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu
1998Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors.
Chi-Keung Luk, Todd C. Mowry
1998Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes.
Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan
1998Effective Cluster Assignment for Modulo Scheduling.
Erik Nystrom, Alexandre E. Eichenberger
1998Evaluating MMX Technology Using DSP and Multimedia Applications.
Ravi Bhargava, Lizy Kurian John, Brian L. Evans, Ramesh Radhakrishnan
1998Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
1998Improving I/O Performance with a Conditional Store Buffer.
Lambert Schaelicke, Al Davis
1998Improving Locality Using Loop and Data Transformations in an Integrated Framework.
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
1998Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms.
Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark
1998Load Latency Tolerance in Dynamically Scheduled Processors.
Srikanth T. Srinivasan, Alvin R. Lebeck
1998Precise Register Allocation for Irregular Architectures.
Timothy Kong, Kent D. Wilken
1998Predicting Indirect Branches via Data Compression.
John Kalamatianos, David R. Kaeli
1998Predictive Techniques for Aggressive Load Speculation.
Glenn Reinman, Brad Calder
1998Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998
James O. Bondi, Jim Smith
1998Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors.
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
1998Simple Vector Microprocessors for Multimedia Applications.
Corinna G. Lee, Mark G. Stoodley
1998Split-path Enhanced Pipeline Scheduling for Loops with Control Flows.
SangMin Shim, Soo-Mook Moon
1998Task Selection for a Multiscalar Processor.
T. N. Vijaykumar, Gurindar S. Sohi
1998The Cascaded Predictor: Economical and Adaptive Branch Target Prediction.
Karel Driesen, Urs Hölzle
1998The YAGS Branch Prediction Scheme.
Avinoam N. Eden, Trevor N. Mudge
1998Understanding the Differences Between Value Prediction and Instruction Reuse.
Avinash Sodani, Gurindar S. Sohi
1998Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures.
Emre Özer, Sanjeev Banerjia, Thomas M. Conte
1998Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures.
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé