MICRO A*

27 papers

YearTitle / Authors
1991A New Technique for Induction Variable Removal.
Haigeng Wang, Alexandru Nicolau, Roni Potasman
1991A Quantitative Analysis of Locality in Dataflow Programs.
William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm
1991ALPS: An Algorithm for Pipeline Data Path Synthesis.
Ramesh Karri, Alex Orailoglu
1991An Analysis of the Information Content of Address Reference Streams.
Jeffrey C. Becker, Arvin Park, Matthew K. Farrens
1991An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300.
Michael A. Schuette, John Paul Shen
1991Architecture and Programming of a VLIW Style Programmable Video Signal Processor.
Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers
1991Code Duplication: An Assist for Global Instruction Scheduling.
David Bernstein, Doron Cohen, Hugo Krawczyk
1991Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
1991DISC: Dynamic Instruction Stream Computer.
Mario Nemirovsky, Forrest Brewer, Roger C. Wood
1991Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.
William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu
1991Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling.
Mark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt
1991Executing Loops on a Fine-Grained MIMD Architecture.
Sunah Lee, Rajiv Gupta
1991GRIP: Graphics Reduced Instruction Processor.
Gautam B. Singh
1991GURPR
Bogong Su, Jian Wang
1991Genetic Algorithms and Instruction Scheduling.
Steven J. Beaty
1991Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors.
Maurício Breternitz Jr., John Paul Shen
1991Increasing User Interaction During High-Level Synthesis.
Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland
1991On Reconfigurable On-Chip Data Caches.
Fredrik Dahlgren, Per Stenström
1991Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991
Yashwant K. Malaiya
1991Register/File/Cache Microarchitecture Study Using VHDL.
Samarina Makhdoom, Daniel Tabak, Richard Auletta
1991Software Pipelining for Transport-Triggered Architectures.
Jan Hoogerbrugge, Henk Corporaal, Hans M. Mulder
1991Software Pipelining: An Evaluation of Enhanced Pipelining.
Reese B. Jones, Vicki H. Allan
1991Strategies for Branch Target Buffers.
Brian K. Bray, Michael J. Flynn
1991The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling.
Michael Butler, Yale N. Patt
1991Two-Level Adaptive Training Branch Prediction.
Tse-Yu Yeh, Yale N. Patt
1991Viewing Instruction Set Design as an Optimization Problem.
Bruce K. Holmer, Alvin M. Despain
1991Workload and Implementation Considerations for Dynamic Base Register Caching.
Matthew K. Farrens, Arvin Park