MICRO A*

45 papers

YearTitle / Authors
201144rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011
Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic
2011A compile-time managed multi-level register file hierarchy.
Mark Gebhart, Stephen W. Keckler, William J. Dally
2011A data layout optimization framework for NUCA-based multicores.
Yuanrui Zhang, Wei Ding, Mahmut T. Kandemir, Jun Liu, Ohyoung Jang
2011A new case for the TAGE branch predictor.
André Seznec
2011A register-file approach for row buffer caches in die-stacked DRAMs.
Gabriel H. Loh
2011A resistive TCAM accelerator for data-intensive computing.
Qing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek
2011A systematic methodology to develop resilient cache coherence protocols.
Konstantinos Aisopos, Li-Shiuan Peh
2011ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer.
Jiaqi Zhang, Weiwei Xiong, Yang Liu, Soyeon Park, Yuanyuan Zhou, Zhiqiang Ma
2011Accelerating microprocessor silicon validation by exposing ISA diversity.
Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González
2011Active management of timing guardband to save energy in POWER7.
Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter
2011Architectural support for secure virtualization under a vulnerable hypervisor.
Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh
2011Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations.
Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa
2011Bundled execution of recurring traces for energy-efficient general purpose processing.
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August
2011CRAM: coded registers for amplified multiporting.
Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti
2011Complementing user-level coarse-grain parallelism with implicit speculative parallelism.
Nikolas Ioannou, Marcelo Cintra
2011CoreRacer: a practical memory race recorder for multicore x86 TSO processors.
Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu
2011Dataflow execution of sequential imperative programs on multicore architectures.
Gagan Gupta, Gurindar S. Sohi
2011Efficiently enabling conventional block sizes for very large die-stacked DRAM caches.
Gabriel H. Loh, Mark D. Hill
2011Encore: low-cost, fine-grained transient fault recovery.
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August
2011FeatherWeight: low-cost optical arbitration with QoS support.
Yan Pan, John Kim, Gokhan Memik
2011Formally enhanced runtime verification to ensure NoC functional correctness.
Ritesh Parikh, Valeria Bertacco
2011Hardware transactional memory for GPU architectures.
Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt
2011Idempotent processor architecture.
Marc de Kruijf, Karthikeyan Sankaralingam
2011Identifying and predicting timing-critical instructions to boost timing speculation.
Jing Xin, Russ Joseph
2011Improving GPU performance via large warps and two-level warp scheduling.
Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt
2011Manager-client pairing: a framework for implementing coherence hierarchies.
Jesse G. Beu, Michel C. Rosier, Thomas M. Conte
2011Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John
2011Multi retention level STT-RAM cache designs with a dynamic refresh scheme.
Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu
2011PACMan: prefetch-aware cache management for high performance caching.
Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
2011Pack & Cap: adaptive DVFS and thread packing under power caps.
Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda
2011Packet chaining: efficient single-cycle allocation for on-chip networks.
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2011Parallel application memory scheduling.
Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt
2011Pay-As-You-Go: low-overhead hard-error correction for phase change memories.
Moinuddin K. Qureshi
2011Preventing PCM banks from seizing too much power.
Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger
2011Proactive instruction fetch.
Michael Ferdman, Cansu Kaynak, Babak Falsafi
2011QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.
Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson
2011Reducing memory interference in multicore systems via application-aware memory channel partitioning.
Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda
2011Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.
Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong
2011Resilient microring resonator based photonic networks.
Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2011SHiP: signature-based hit predictor for high performance caching.
Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
2011SIMD re-convergence at thread frontiers.
Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili
2011System-level integrated server architectures for scale-out datacenters.
Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi
2011The NoX router.
Mitchell Hayenga, Mikko H. Lipasti
2011Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.
Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt
2011TransCom: transforming stream communication for load balance and efficiency in networks-on-chip.
Ahmed H. Abdel-Gawad, Mithuna Thottethodi