MICRO A*

46 papers

YearTitle / Authors
201043rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA
2010A Dynamically Adaptable Hardware Transactional Memory.
Marc Lupon, Grigorios Magklis, Antonio González
2010A Predictive Model for Dynamic Microarchitectural Adaptivity Control.
Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F. P. O'Boyle
2010ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory.
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman
2010AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors.
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout
2010Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies.
Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer
2010Adaptive Flow Control for Robust Performance and Energy.
Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar
2010Adaptive and Speculative Slack Simulations of CMPs on CMPs.
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois
2010Architectural Support for Fair Reader-Writer Locking.
Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero
2010AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection.
Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas
2010Automatic Parallelization in a Binary Rewriter.
Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua
2010Combating Aging with the Colt Duty Cycle Equalizer.
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti
2010Efficient Selection of Vector Instructions Using Dynamic Programming.
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
2010Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John
2010Erasing Core Boundaries for Robust and Configurable Performance.
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke
2010Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.
Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
2010Fractal Coherence: Scalably Verifiable Cache Coherence.
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
2010Hardware Support for Relaxed Concurrency Control in Transactional Memory.
Utku Aydonat, Tarek S. Abdelrahman
2010Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels.
Michael Steffen, Joseph Zambreno
2010InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing.
Adrian Nistor, Darko Marinov, Josep Torrellas
2010LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.
Jin Ouyang, Yuan Xie
2010Many-Thread Aware Prefetching Mechanisms for GPGPU Applications.
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc
2010Memory Latency Reduction via Thread Throttling.
Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang
2010Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors.
Guoping Long, Diana Franklin, Susmit Biswas, Pablo J. Ortiz, Jason Oberg, Dongrui Fan, Frederic T. Chong
2010Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson
2010Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches.
Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu
2010Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs.
Michael Mihn-Jong Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee
2010Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks.
Minseon Ahn, Eun Jung Kim
2010ReMAP: A Reconfigurable Heterogeneous Multicore Architecture.
Matthew A. Watkins, David H. Albonesi
2010Register Cache System Not for Latency Reduction Purpose.
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2010SAFER: Stuck-At-Fault Error Recovery for Memories.
Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee
2010SD3: A Scalable Approach to Dynamic Data-Dependence Profiling.
Minjang Kim, Hyesoon Kim, Chi-Keung Luk
2010STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches.
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
2010Sampling Dead Block Prediction for Last-Level Caches.
Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez
2010Scalable Speculative Parallelization on Commodity Clusters.
Hanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, David I. August
2010ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment.
Xuehai Qian, Wonsun Ahn, Josep Torrellas
2010Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai
2010Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors.
Shekhar Srikantaiah, Mahmut T. Kandemir
2010Task Superscalar: An Out-of-Order Task Pipeline.
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2010The ZCache: Decoupling Ways and Associativity.
Daniel Sánchez, Christos Kozyrakis
2010Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
2010Throughput-Effective On-Chip Networks for Manycore Accelerators.
Ali Bakhoda, John Kim, Tor M. Aamodt
2010Tolerating Concurrency Bugs Using Transactions as Lifeguards.
Jie Yu, Satish Narayanasamy
2010Understanding the Energy Consumption of Dynamic Random Access Memories.
Thomas Vogelsang
2010Virtual Snooping: Filtering Snoops in Virtualized Multi-cores.
Daehoon Kim, Hwanju Kim, Jaehyuk Huh
2010Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.
Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks