MICRO A*

55 papers

YearTitle / Authors
200942st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA
David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez
2009A case for dynamic frequency tuning in on-chip networks.
Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009A microarchitecture-based framework for pre- and post-silicon power delivery analysis.
Mahesh Ketkar, Eli Chiprout
2009A tagless coherence directory.
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos
2009Adaptive line placement with the
Dyer Rolán, Basilio B. Fraguela, Ramon Doallo
2009An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato
2009Application-aware prioritization mechanisms for on-chip networks.
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2009Architecting a chunk-based memory race recorder in modern CMPs.
Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai
2009BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.
Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong
2009Characterizing and mitigating the impact of process variations on phase change based memory systems.
Wangyuan Zhang, Tao Li
2009Characterizing flash memory: anomalies, observations, and applications.
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf
2009Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2009Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.
Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel
2009Complexity effective memory access scheduling for many-core accelerator architectures.
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
2009Control flow obfuscation with information flow tracking.
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-Chung Yew
2009Coordinated control of multiple prefetchers in multi-core systems.
Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt
2009DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage.
Changhee Jung, Nathan Clark
2009ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem.
Ciji Isen, Lizy Kurian John
2009EazyHTM: eager-lazy hardware transactional memory.
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero
2009Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.
Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Bülent Abali
2009Execution leases: a hardware-supported mechanism for enforcing strong non-interference.
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood
2009Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.
Gabriel H. Loh
2009Finding concurrency bugs with context-aware communication graphs.
Brandon Lucia, Luis Ceze
2009Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.
Sangyeun Cho, Hyunjin Lee
2009Improving cache lifetime reliability at ultra-low voltages.
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2009Improving memory bank-level parallelism in the presence of prefetching.
Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt
2009In-network coherence filtering: snoopy coherence without broadcasts.
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
2009Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.
Alex Shye, Benjamin Scholbrock, Gokhan Memik
2009Light speed arbitration and flow control for nanophotonic interconnects.
Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti
2009Light64: lightweight hardware support for data race detection during systematic testing of parallel programs.
Adrian Nistor, Darko Marinov, Josep Torrellas
2009Low Vccmin fault-tolerant cache with highly predictable performance.
Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González
2009Low-cost router microarchitecture for on-chip networks.
John Kim
2009McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.
Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
2009Multiple clock and voltage domains for chip multi processors.
Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser
2009Offline symbolic analysis for multi-processor execution replay.
Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang, Cristiano Pereira
2009Optimizing shared cache behavior of chip multiprocessors.
Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk
2009Ordering decoupled metadata accesses in multiprocessors.
Hari Kannan
2009POWER7 multi-core processor design.
Balaram Sinharoy
2009Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.
Hyunchul Park, Yongjun Park, Scott A. Mahlke
2009Portable compiler optimisation across embedded programs and microarchitectures using machine learning.
Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle
2009Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.
Boris Grot, Stephen W. Keckler, Onur Mutlu
2009Proactive transaction scheduling for contention management.
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2009Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.
Mainak Chaudhuri
2009Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping.
Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
2009Reducing peak power with a table-driven adaptive processor core.
Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar
2009SCARAB: a single cycle adaptive routing and bufferless network.
Mitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti
2009SHARP control: controlled shared cache management in chip multiprocessors.
Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang
2009The BubbleWrap many-core: popping cores for sequential acceleration.
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
2009Tree register allocation.
Hongbo Rong
2009Tribeca: design for PVT variations with local recovery and fine-grained adaptation.
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks
2009Using a configurable processor generator for computer architecture prototyping.
Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz
2009Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang
2009Why design must change: rethinking digital design.
Mark Horowitz
2009ZerehCache: armoring cache architectures in high defect density technologies.
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke
2009mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.
Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve