MICRO A*

43 papers

YearTitle / Authors
200841st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy
2008A distributed processor state management architecture for large-window processors.
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero
2008A novel cache architecture with enhanced performance and security.
Zhenghong Wang, Ruby B. Lee
2008A performance-correctness explicitly-decoupled architecture.
Alok Garg, Michael C. Huang
2008A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.
Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood
2008Adaptive data compression for high-performance low-power on-chip networks.
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
2008Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.
David E. Shaw
2008CPR: Composable performance regression for scalable multiprocessor models.
Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks
2008Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.
Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger
2008Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.
Ramazan Bitirgen, Engin Ipek, José F. Martínez
2008Copy or Discard execution model for speculative parallelization on multicores.
Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta
2008Dependence-aware transactional memory for increased concurrency.
Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel
2008EVAL: Utilizing processors with variation-induced timing errors.
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
2008Efficient unicast and multicast support for CMPs.
Samuel Rodrigo, José Flich, José Duato, Mark Hummel
2008Evaluating the effects of cache redundancy on profit.
Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
2008Facelift: Hiding and slowing down aging in multicores.
Abhishek Tiwari, Josep Torrellas
2008From SODA to scotch: The evolution of a wireless baseband processor.
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner
2008Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs.
Xi E. Chen, Tor M. Aamodt
2008Implementing high availability memory with a duplication cache.
Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan
2008Low-power, high-performance analog neural branch prediction.
Renée St. Amant, Daniel A. Jiménez, Doug Burger
2008Microarchitecture in the system-level integration era.
Charles R. Moore
2008Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.
Wangyuan Zhang, Tao Li
2008Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu
2008NBTI tolerant microarchitecture design in the presence of process variation.
Xin Fu, Tao Li, José A. B. Fortes
2008Notary: Hardware techniques to enhance signatures.
Luke Yen, Stark C. Draper, Mark D. Hill
2008Online design bug detection: RTL analysis, flexible mechanisms, and evaluation.
Kypros Constantinides, Onur Mutlu, Todd M. Austin
2008Power reduction of CMP communication networks via RF-interconnects.
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam
2008Power to the people: Leveraging human physiological traits to control microprocessor frequency.
Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick
2008Prefetch-Aware DRAM Controllers.
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
2008Reconfigurable energy efficient near threshold cache architectures.
Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner
2008Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer.
Livio Soares, David K. Tam, Michael Stumm
2008SHARK: Architectural support for autonomic protection against stealth by rootkit exploits.
Vikas R. Vasisht, Hsien-Hsin S. Lee
2008Shapeshifter: Dynamically changing pipeline width and speed to address process variations.
Eric Chun, Zeshan Chishti, T. N. Vijaykumar
2008Strategies for mapping dataflow blocks to distributed hardware.
Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley
2008Temporal instruction fetch streaming.
Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos
2008Testudo: Heavyweight security analysis via statistical sampling.
Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie
2008The StageNet fabric for constructing resilient multicore systems.
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke
2008Token flow control.
Amit Kumar, Li-Shiuan Peh, Niraj K. Jha
2008Token tenure: PATCHing token counting using directory-based cache coherence.
Arun Raghavan, Colin Blundell, Milo M. K. Martin
2008Toward a multicore architecture for real-time ray-tracing.
Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, William R. Mark
2008Tradeoffs in designing accelerator architectures for visual computing.
Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel
2008Verification of chip multiprocessor memory systems using a relaxed scoreboard.
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
2008Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti