MICRO A*

36 papers

YearTitle / Authors
200740th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA
2007A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.
Jason Zebchuk, Elham Safi, Andreas Moshovos
2007A Framework for Providing Quality of Service in Chip Multi-Processors.
Fei Guo, Yan Solihin, Li Zhao, Ravishankar R. Iyer
2007A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs.
William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe
2007Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
2007Composable Lightweight Processors.
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
2007Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures.
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke
2007Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow.
Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt
2007Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.
Francisco J. Mesa-Martinez, Jose Renau
2007Emulating Optimal Replacement with a Shepherd Cache.
Kaushik Rajan, Ramaswamy Govindarajan
2007FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators.
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
2007Flattened Butterfly Topology for On-Chip Networks.
John Kim, James D. Balfour, William J. Dally
2007Global Multi-Threaded Instruction Scheduling.
Guilherme Ottoni, David I. August
2007Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.
Stephen Hines, David B. Whalley, Gary S. Tyson
2007Impact of Cache Coherence Protocols on the Processing of Network Traffic.
Amit Kumar, Ram Huggahalli
2007Implementing Signatures for Transactional Memory.
Daniel Sánchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam
2007Informed Microarchitecture Design Space Exploration Using Workload Dynamics.
Chang-Burm Cho, Wangyuan Zhang, Tao Li
2007Leveraging 3D Technology for Improved Reliability.
Niti Madan, Rajeev Balasubramonian
2007Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications.
Yuan Chou
2007Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle
2007Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing.
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
2007Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
2007Optimal versus Heuristic Global Code Scheduling.
Sebastian Winkel
2007Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2007Penelope: The NBTI-Aware Processor.
Jaume Abella, Xavier Vera, Antonio González
2007Process Variation Tolerant 3T1D-Based Cache Architectures.
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks
2007Revisiting the Sequential Programming Model for Multi-Core.
Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. August
2007Scavenger: A New Last Level Cache Architecture with Global Block Priority.
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
2007Self-calibrating Online Wearout Detection.
Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
2007Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs.
Mrinmoy Ghosh, Hsien-Hsin S. Lee
2007Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation.
Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco
2007Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.
Onur Mutlu, Thomas Moscibroda
2007The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration.
Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman
2007Time Interpolation: So Many Metrics, So Few Registers.
Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan
2007Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors.
Karin Strauss, Xiaowei Shen, Josep Torrellas
2007Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly.
Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin