| 2003 | A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin |
| 2003 | Beating in-order stalls with "flea-flicker" two-pass pipelining. Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
| 2003 | Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan |
| 2003 | Comparing Program Phase Detection Techniques. Ashutosh S. Dhodapkar, James E. Smith |
| 2003 | Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero |
| 2003 | Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar |
| 2003 | Efficient Memory Integrity Verification and Encryption for Secure Processors. G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas |
| 2003 | Exploiting Value Locality in Physical Register Files. Saisanthosh Balakrishnan, Gurindar S. Sohi |
| 2003 | Fast Path-Based Neural Branch Prediction. Daniel A. Jiménez |
| 2003 | Fast Secure Processor for Inhibiting Software Piracy and Tampering. Jun Yang, Youtao Zhang, Lan Gao |
| 2003 | Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. Enric Gibert, F. Jesús Sánchez, Antonio González |
| 2003 | Generational Cache Management of Code Traces in Dynamic Optimization Systems. Kim M. Hazelwood, Michael D. Smith |
| 2003 | Hardware Support for Control Transfers in Code Caches. Ho-Seop Kim, James E. Smith |
| 2003 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach |
| 2003 | IPStash: a Power-Efficient Memory Architecture for IP-lookup. Stefanos Kaxiras, Georgios Keramidas |
| 2003 | In Memory of Bob Rau. Michael S. Schlansker |
| 2003 | Instruction Replication for Clustered Microarchitectures. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli |
| 2003 | LLVA: A Low-level Virtual Instruction Set Architecture. Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke |
| 2003 | Macro-op Scheduling: Relaxing Scheduling Loop Constraints. Ilhyun Kim, Mikko H. Lipasti |
| 2003 | Microarchitecture on the MOSFET Diet. Kerry Bernstein |
| 2003 | Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. Se-Hyun Yang, Babak Falsafi |
| 2003 | Optimum Power/Performance Pipeline Depth. Allan Hartstein, Thomas R. Puzak |
| 2003 | Power-driven Design of Router Microarchitectures in On-chip Networks. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik |
| 2003 | Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003 |
| 2003 | Processor Acceleration Through Automated Instruction Set Customization. Nathan Clark, Hongtao Zhong, Scott A. Mahlke |
| 2003 | Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge |
| 2003 | Reducing Design Complexity of the Load/Store Queue. Il Park, Chong-liang Ooi, T. N. Vijaykumar |
| 2003 | Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. Canturk Isci, Margaret Martonosi |
| 2003 | Scalable Hardware Memory Disambiguation for High ILP Processors. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler |
| 2003 | Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen |
| 2003 | Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen |
| 2003 | TLC: Transmission Line Caches. Bradford M. Beckmann, David A. Wood |
| 2003 | The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen |
| 2003 | The Reconfigurable Streaming Vector Processor (RSVPTM). Silviu M. S. A. Chiricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi |
| 2003 | Universal Mechanisms for Data-Parallel Architectures. Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger |
| 2003 | Using Interaction Costs for Microarchitectural Bottleneck Analysis. Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn |
| 2003 | VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy |
| 2003 | WaveScalar. Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin |