| 2000 | A framework for dynamic energy efficiency and temperature management. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas |
| 2000 | A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. Zhao Zhang, Zhichun Zhu, Xiaodong Zhang |
| 2000 | A static power model for architects. J. Adam Butts, Gurindar S. Sohi |
| 2000 | A study of slipstream processors. Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg |
| 2000 | A whole new ballgame - supercomputing on two AA batteries (keynote session). David Baker |
| 2000 | Accurate and efficient predicate analysis with binary decision diagrams. John W. Sias, Wen-mei W. Hwu, David I. August |
| 2000 | An integrated approach to accelerate data and predicate computations in hyperblocks. Alexandre E. Eichenberger, Waleed Meleis, Suman Maradani |
| 2000 | Breathing life into a paper tiger (keynote session). Darrell Boggs |
| 2000 | Calpa: a tool for automating selective dynamic compilation. Markus Mock, Craig Chambers, Susan J. Eggers |
| 2000 | Compiler controlled value prediction using branch predictor based confidence. Eric Larson, Todd M. Austin |
| 2000 | Defect tolerant molecular electronics: algorithms, architectures, and atoms. Phil Keukes |
| 2000 | Dynamic zero compression for cache energy reduction. Luis Villa, Michael Zhang, Krste Asanovic |
| 2000 | Eager writeback - a technique for improving bandwidth utilization. Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens |
| 2000 | Efficient checker processor design. Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin |
| 2000 | Efficient conditional operations for data-parallel architectures. Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany |
| 2000 | Flexible hardware acceleration for multimedia oriented microprocessors. Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man |
| 2000 | Frequent value compression in data caches. Jun Yang, Youtao Zhang, Rajiv Gupta |
| 2000 | Improving BTB performance in the presence of DLLs. Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson |
| 2000 | Increasing the size of atomic instruction blocks using control flow assertions. Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum |
| 2000 | Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. Amirali Baniasadi, Andreas Moshovos |
| 2000 | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas |
| 2000 | Modulo scheduling for a fully-distributed clustered VLIW architecture. F. Jesús Sánchez, Antonio González |
| 2000 | On pipelining dynamic instruction scheduling logic. Jared Stark, Mary D. Brown, Yale N. Patt |
| 2000 | Performance improvement with circuit-level speculation. Tong Liu, Shih-Lien Lu |
| 2000 | PipeRench implementation of the instruction path coprocessor. Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen |
| 2000 | Predictor-directed stream buffers. Timothy Sherwood, Suleyman Sair, Brad Calder |
| 2000 | Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000 Andrew Wolfe, Michael S. Schlansker |
| 2000 | Reducing wire delay penalty through value prediction. Joan-Manuel Parcerisa, Antonio González |
| 2000 | Register integration: a simple and efficient implementation of squash reuse. Amir Roth, Gurindar S. Sohi |
| 2000 | Relational profiling: enabling thread-level parallelism in virtual machines. Timothy H. Heil, James E. Smith |
| 2000 | Silent stores for free. Kevin M. Lepak, Mikko H. Lipasti |
| 2000 | The impact of delay on the design of branch predictors. Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin |
| 2000 | The store-load address table and speculative register promotion. Matt Postiff, David A. Greene, Trevor N. Mudge |
| 2000 | Two-level hierarchical register file organization for VLIW processors. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
| 2000 | Very low power pipelines using significance compression. Ramon Canal, Antonio González, James E. Smith |