MICRO A*

43 papers

YearTitle / Authors
1992A VLIW architecture for optimal execution of branch-intensive loops.
Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib
1992A comprehensive instruction fetch mechanism for a processor supporting speculative execution.
Tse-Yu Yeh, Yale N. Patt
1992A dynamic-programming technique for compacting loops.
Steven R. Vegdahl
1992A new approach to schedule operations across nested-ifs and nested-loops.
Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
1992A non-deterministic scheduler for a software pipelining compiler.
Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1992A shape matching approach for scheduling fine-grained parallelism.
Brian A. Malloy, Rajiv Gupta, Mary Lou Soffa
1992An efficient architecture for loop based data preloading.
William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo
1992An efficient resource-constrained global scheduling technique for superscalar and VLIW processors.
Soo-Mook Moon, Kemal Ebcioglu
1992An investigation of the performance of various dynamic scheduling techniques.
Michael Butler, Yale N. Patt
1992An out-of-order superscalar processor with speculative execution and fast, precise interrupts.
Harry Dwyer, Hwa C. Torng
1992Branch merging for effective exploitation of instruction-level parallelism.
Chien-Ming Chen, Yunn Yen Chen, Chung-Ta King
1992Code generation schema for modulo scheduled loops.
B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
1992Code scheduling for VLIW/superscalar processors with limited register files.
Tokuzo Kiyohara, John C. Gyllenhaal
1992Controlling and sequencing a heavily pipelined floating-point operator.
André Seznec, Karl Courtel
1992Data path issues in a highly concurrent machine.
Augustus K. Uht, Darin B. Johnson
1992Dominator-path scheduling: a global scheduling method.
Philip H. Sweany, Steven J. Beaty
1992Effective compiler support for predicated execution using the hyperblock.
Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann
1992Enhanced modulo scheduling for loops with conditional branches.
Nancy J. Warter, Grant E. Haab, Krishna Subramanian, John W. Bockhaus
1992Enhanced region scheduling on a program dependence graph.
V. H. Allen, J. Janardhan, R. M. Lee, M. Srinivas
1992Executing compressed programs on an embedded RISC architecture.
Andrew Wolfe, Alex Chanin
1992Exploiting instruction-level parallelism with the conjugate register file scheme.
Meng-Chou Chang, Feipei Lai, Rung-Ji Shang
1992Exploiting instruction-level parallelism: the multithreaded approach.
Philip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar
1992Interlock collapsing ALU for increased instruction-level parallelism.
Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis
1992Limitation of superscalar microprocessor performance.
Thang Tran, Chuan-lin Wu
1992Lookahead scheduling.
Steven J. Beaty
1992MISC: a Multiple Instruction Stream Computer.
Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
1992Microarchitecture support for dynamic scheduling of acyclic task graphs.
Carl J. Beckmann, Constantine D. Polychronopoulos
1992Modifying VM hardware to reduce address pin requirements.
Matthew K. Farrens, Arvin Park, Gary S. Tyson
1992On the instruction-level characteristics of scalar code in highly-vectorized scientific applications.
Sriram Vajapeyam, Wei-Chung Hsu
1992On the limits of program parallelism and its smoothability.
Kevin B. Theobald, Guang R. Gao, Laurie J. Hendren
1992Ordering functions for improving memory reference locality in a shared memory multiprocessor system.
Youfeng Wu
1992Partitioned register files for VLIWs: a preliminary analysis of tradeoffs.
Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau
1992Performance analysis and design methodology for a scalable superscalar architecture.
Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh
1992Performance evaluation of instruction scheduling on the IBM RISC System/6000.
David Bernstein, Doron Cohen, Yuval Lavon, Vladimir Rainish
1992Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992
Wen-mei W. Hwu
1992Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors.
Manoj Franklin, Gurindar S. Sohi
1992StaCS: a Static Control Superscalar architecture.
Benoît Dupont de Dinechin
1992Stride directed prefetching in scalar processors.
John W. C. Fu, Janak H. Patel, Bob L. Janssens
1992The effect of page allocation on caches.
William L. Lynch, Brian K. Bray, Michael J. Flynn
1992Toward zero-cost branches using instruction registers.
Kent D. Wilken, David W. Goodwin
1992Tradeoffs in processor/memory interfaces for superscalar processors.
Thomas M. Conte
1992Translation hint buffers to reduce access time of physically-addressed instruction caches.
Brian K. Bray, Michael J. Flynn
1992Y-Pipe: a conditional branching scheme without pipeline delays.
Michael J. Knieser, Christos A. Papachristou