ITC A

62 papers

YearTitle / Authors
2024A Cell-aware Transistor State Stress Model and its Application for Quality Measurement.
Stephan Eggersglüß, Andreas Glowatz
2024A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation.
Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction.
Mehul D. Shroff, Nguyen Nguyen, Kiran Sunny Thota
2024A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits.
Daniel Adjei, Emmanuel Nti Darko, Degang Chen
2024A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS.
Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun
2024A graph-based algorithm for NVM address decoders testing.
Pierre Scaramuzza, Thomas Kern, Matteo Coppetta, Alessandro Grossi, Rudolf Ullmann
2024AI-Enabled Board Level Vibration Testing: Unveiling The Physics of Degradation.
Varun Thukral, Chen He, Rebecca Chen, Letian Zhang, Romuald Roucou, Michiel van Soestbergen, Jeroen J. M. Zaal, Rene Rongen, Willem D. van Driel, G. Q. Zhang
2024Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage.
Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey
2024Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence.
C. W. Lin, P. C. Tsao, Ross Lee, Khim Koh, Y. J. Ting, Jennifer Hsiao, C. T. Lai, T. H. Lee
2024Cross-Layer Reliability Evaluation of In-Memory Similarity Computation.
Ali Nezhadi, Mahta Mayahinia, Mehdi B. Tahoori
2024Defect Analysis for FeFETs using a Compact Model.
Dhruv Thapar, Arjun Chaudhuri, Kai Ni, Krishnendu Chakrabarty
2024Defects, Fault Modeling, and Test Development Framework for FeFETs.
Changhao Wang, Sicong Yuan, Hanzhi Xun, Chaobo Li, Mottaqiallah Taouil, Moritz Fieback, Danyang Chen, Xiuyan Li, Lin Wang, Riccardo Cantoro, Chujun Yin, Said Hamdioui
2024Delay Monitoring Under Different PVT Corners for Test and Functional Operation.
Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024Design-for-Test for Silicon Photonic Circuits.
Pratishtha Agnihotri, Priyank Kalla, Steve Blair
2024Deterministic In-Fleet Scan Test for a Cloud Computing Platform.
Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer
2024Diagnosis of Defects on Global Signals.
Xinyang Zhao, Baohua Wang, Yin Zhang, Weiming Zhang, Xiaotian Ding, Yu Huang
2024Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies.
Jaehoon Lee, HyeonUk Son, Seohyun Kang, Dahyun Kang, Dongkwan Han, Jongsin Yun, Artur Pogiel, Etienne Racine, Krzysztof Jurga, Lori Schramm, Martin Keim
2024Digital Scan and ATPG for Analog Circuits.
Stephen Sunter, Krzysztof Jurga
2024E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry.
Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty
2024Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge Devices.
Geancarlo Abich, Ricardo Augusto da Luz Reis, Luciano Ost
2024Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor.
Suriyaprakash Natarajan, Chaitali S. Oak, Vijay Kakollu, Nipun Chaplot, Soham Roy, Apurva Lonkar, Gerardo J. Perfecto Reyes
2024Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips.
Yi-Chun Huang, Pei-Yun Lin, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee
2024Electrical Stimulus Based Calibration of MEMS Accelerometer.
Ishaan Bassi, Sule Ozev
2024Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States.
Anlin Liu, Tianyao Lu, Yuhao Xi, Yangfan Liu, Peng Liu
2024Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques.
Aleksa Deric, Kyle Mitard, Shahin Tajik, Daniel E. Holcomb
2024FAT-RABBIT: Fault-Aware Training towards Robustness AgainstBit-flip Based Attacks in Deep Neural Networks.
Hossein Pourmehrani, Javad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash, Naghmeh Karimi
2024From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel.
Brian Pajak, Pankaj Pant, Vidya Neerkundar
2024Functional State Extraction using Scan DFT.
Ilya Wagner, Pankaj Pant, Arani Sinha
2024Functionally-Possible Gate-Exhaustive Bridging Faults.
Irith Pomeranz
2024Generation and Quality Evaluation of Synthetic Process Control Monitoring Data.
Matthew Nigh, John M. Carulli, Yiorgos Makris
2024Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests.
Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora
2024High-Bandwidth IJTAG over SSN.
Jonathan Gaudet, Jan Burchard, Matthias Kampmann, Jean-François Côté, Tim Callahan, Hung Ho Chai, Ivy Ee Hsia Lim, Lori Schramm, Olga Przybysz, Marta Stepniewska, Sascha Ochsenknecht, Michal Olejarz, Martin Keim
2024IEEE International Test Conference, ITC 2024, San Diego, CA, USA, November 3-8, 2024
2024Identifying Undetectable Defects Using Equivalence Checking.
Lars Hedrich, Inga Abel, Jaafar Mejri, Vladimir A. Zivkovic
2024LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets.
Alan S.-M. Liu, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh
2024Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation.
Leon Li, Alex Orailoglu
2024MBIST-based MRAM defect screening for safety-critical applications.
Sina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi B. Tahoori
2024Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.
Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
2024Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard.
Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar
2024Power-Aware Test Scheduling for Memory BIST.
Albert Au, Michal Kçpinski, Makary Orczyk, Artur Pogiel
2024Predictive Testing for Aging in SRAMs and Mitigation.
Yunkun Lin, Mingye Li, Sandeep Gupta
2024Probe Card Ground Noise Canceling Circuit.
Seongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi, ChanYeol Park, Sunyong Park, Woonphil Yang
2024Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs.
Hanzhi Xun, Moritz Fieback, Mohammad Amin Yaldagard, Sicong Yuan, Erbing Hua, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui
2024SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Ashish Reddy Bommana, Farshad Firouzi, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
2024SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits.
Galib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi
2024Safety-Guided Test Generation for Structural Faults.
Xuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji
2024Scalable BIST for Linearity Testing of Sigma-Delta Modulators.
Krishna Pramod Madabhushi, Trevor LaBanz, Sudip Dandnaik, Eslam Hag
2024Scan SerDes
Saurabh Upadhyay, Ahmet Tokuz
2024Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs.
Hiroyuki Iwata, Mahmoud AbdAlwahab, Ron Press, Ohki Sugiura
2024Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test.
Chi Lai, Shi-Yu Huang
2024TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering.
Suhasini Komarraju, Mohamed Mejri, Abhijit Chatterjee, Suriyaprakash Natarajan, Prashant Goteti
2024Test Data Encryption with a New Stream Cipher.
Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
Sicong Yuan, Hanzhi Xun, Woojin Kim, Siddharth Rao, Erik Jan Marinissen, Sebastien Couet, Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui
2024Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects.
Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2024Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip.
Corrado De Sio, Luca Sterpone
2024Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation.
Dipali Jain, Guangwei Zhao, Rajesh Datta, Kaveh Shamsi
2024Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults.
Soham Roy, Vishwani D. Agrawal
2024Virtual Test Development Using Pre-Silicon Verification Environment.
E. Aderholz, Q. Atol, B. Baptist, R. Holzner, R. Ignacio, V. Kamanuri, A. Kun, K. Ma, B. Mariacher, O. Pfabigan, A. Przybilla, D. Samardzic, F. Schlagbauer, M. Schleicher, J. P. Valiente, E. Vargas, K. Vinod, O. Zikulnig
2024WM-Graph: Graph-Based Approach for Wafermap Analytics.
Min Jian Yang, Yueling Jenny Zeng, Li-C. Wang
2024Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant.
Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
2024Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification.
Abhishek Kumar Mishra, Suman Kumar, Anush Niranjan Lingamoorthy, Anup Das, Nagarajan Kandasamy
2024qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors.
Yen-Wei Li, Cheng-Yun Hsieh, Meng-Chen Wu, James Chien-Mo Li