ITC A

52 papers

YearTitle / Authors
20213.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment.
Seongkwan Lee, Minho Kang, Cheolmin Park, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim
2021A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
Jonti Talukdar, Siyuan Chen, Amitabh Das, Sohrab Aftabjahani, Peilin Song, Krishnendu Chakrabarty
2021A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors.
Julia Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel
2021A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators.
Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann
2021AAA: Automated, On-ATE AI Debug of Scan Chain Failures.
Chris Nigh, Gaurav Bhargava, Ronald D. Blanton
2021ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph.
Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen
2021Accessing general IEEE Std. 1687 networks via functional ports.
Erik Larsson, Prathamesh Murali, Ziling Zhang
2021Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies.
Stephen Traynor, Chen He, Y. Y. Yu, Ken Klein
2021Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards.
Mengyun Liu, Krishnendu Chakrabarty
2021Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement.
Xin Huang, Min Qin, Ruosheng Xu, Cheng Chen, Shangling Jui, Zhihao Ding, Pengyun Li, Yu Huang
2021An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designs.
Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer
2021Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory.
Mahta Mayahinia, Christopher Münch, Mehdi B. Tahoori
2021Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation.
Franziska Mayer, Christian Schott, Enrico Billich, Saeid Yazdani, Ulrich Heinkel, Georg Daler, Bernhard Ruf, Ricardo Pannuzzo, Wolfgang Dickenscheid
2021Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration.
Muslum Emir Avci, Sule Ozev
2021Brain-Inspired Computing for Wafer Map Defect Pattern Classification.
Paul R. Genssler, Hussam Amrouch
2021Characterizing Corruptibility of Logic Locks using ATPG.
Danielle Duvalsaint, R. D. Shawn Blanton
2021Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation.
Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz
2021Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Siddarth Madala, Abhishek Kumar Dubey, Krishnendu Chakrabarty
2021Efficient Functional In-Field Self-Test for Deep Learning Accelerators.
Yi He, Takumi Uezono, Yanjing Li
2021Exploiting Application Tolerance for Functional Safety.
V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur
2021Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles.
Chandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee
2021IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021
2021Impeccable Circuits III.
Shahram Rasoolzadeh, Aein Rezaei Shahmirzadi, Amir Moradi
2021Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization.
Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava
2021Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis.
Sergej Meschkov, Dennis R. E. Gnad, Jonas Krautter, Mehdi B. Tahoori
2021LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment.
M. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2021Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
2021MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification.
Yueling Jenny Zeng, Li-C. Wang, Chuanhe Jay Shan
2021Machine Learning for Circuit Aging Estimation under Workload Dependency.
Florian Klemme, Hussam Amrouch
2021Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning.
Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
2021Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs.
Jorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew
2021On Reduction of Deterministic Test Pattern Sets.
Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2021On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums.
Ching-Yuan Chen, Krishnendu Chakrabarty
2021Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry.
Yang Shang, Makoto Shinohara, Eiji Kato, Masaichi Hashimoto, Joanna Kiljan
2021Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits.
Tommaso Melis, Emmanuel Simeu, Luc Saury, Etienne Auvray
2021Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies.
Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2021Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture.
Bambang Suparjo, Jugantor Chetia, Ankit R. Shah
2021Security EDA Extension through P1687.1 and 1687 Callbacks.
Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale
2021Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.
Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning.
Hanbin Hu, Chen He, Peng Li
2021Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach.
Chenwei Liu, Jie Ou
2021Study on High-Accuracy and Low-Cost Recycled FPGA Detection.
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2021Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer.
Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi
2021SymbA: Symbolic Execution at C-level for Hardware Trojan Activation.
Arash Vafaei, Nick Hooten, Mark Tehranipoor, Farimah Farahmandi
2021Systematic Hardware Error Identification and Calibration for Massive Multisite Testing.
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021Testability-Aware Low Power Controller Design with Evolutionary Learning.
Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu
2021Testability-Enhancing Resynthesis of Reconfigurable Scan Networks.
Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich
2021Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions.
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2021The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack.
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui
2021Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels.
Chenwei Liu, Qiaoyue Tang
2021WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques.
Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou
2021Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process.
Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki