ITC A

73 papers

YearTitle / Authors
201917th IEEE East-West Design and Test Symposium.
Yervant Zorian, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova
2019A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips.
Andrea Floridia, Davide Piumatti, Annachiara Ruospo, Ernesto Sánchez, Sergio de Luca, Rosario Martorana
2019A Framework for Design of Self-Repairing Digital Systems.
Jingchi Yang, David C. Keezer
2019A Hybrid Space Compactor for Adaptive X-Handling.
Mohammad Urf Maaz, Alexander Sprenger, Sybille Hellebrand
2019A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces.
Kiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida
2019A New Test Method for the Large Current Magnetic Sensors.
Toshiyuki Omuro, Shigeo Nakamura Surname, Takashi Kimura, Kiyokawa Omuro
2019Advanced Burn-In - An Optimized Product Stress and Test Flow for Automotive Microcontrollers.
Chen He
2019An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures.
Adit D. Singh
2019An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.
Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
2019An Overview of the International Microprocessor/ SoC Test, Security and Validation (MTV)Workshop.
Magdy Abadir, Sohrab Aftabjahani
2019An Overview of the International Verification and Security Workshop (IVSW).
Magdy Abadir, Sohrab Aftabjahani
2019Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library.
Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen
2019Applications of Hierarchical Test.
Kelly Ockunzzi, Richard Grupp, Brion Keller, Mark Taylor, Sreekanth Pai, Greeshma Jayakumar
2019Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs.
Wim Dobbelaere, Frederik Colle, Anthony Coyette, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen
2019Armenia: Communicating to World Community in Electronic Test and Design.
Samvel K. Shoukourian, Yuri Shoukourian, Vladimir Sahakyan
2019Asian Test Symposium - Past, Present and Future -.
Michiko Inoue, Xiaowei Li, Cheng-Wen Wu
2019Breaking Analog Locking Techniques via Satisfiability Modulo Theories.
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2019Built-in self-test and self-calibration for analog and mixed signal circuits.
Tao Chen, Degang Chen
2019Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee
2019Characterization of Locked Combinational Circuits via ATPG.
Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton
2019China Test Conference (CTC) - Extending the Global Test Forum to China.
Huawei Li, Xiaowei Li, Yinhe Han
2019Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation.
Irith Pomeranz
2019DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips.
Ahmed M. Y. Ibrahim, Hans G. Kerkhoff
2019Deploying A Machine Learning Solution As A Surrogate.
Chuanhe Jay Shan, Ahmed Wahba, Li-C. Wang, Nik Sumikawa
2019Device-Aware Test: A New Test Approach Towards DPPB Level.
Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui
2019Effectively Using Machine Learning to Expedite System Level Test Failure Debug.
Luis D. Rojas, Kevin Hess, Christina Carter-Brown
2019Efficiency Measurement Method for Fully Integrated Voltage Regulators used in 4
Gerhard Schrom, Michael J. Hill, Sarath Makala, Ravi Sankar Vunnam, Arun Krishnamoorthy, Ryan Ferguson
2019Efficient Analog Defect Simulation.
Stephen Sunter
2019FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging.
Cheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen
2019FPGA Bitstream Security: A Day in the Life.
Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, Mark Tehranipoor
2019Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviors.
Zhanwei Zhong, Krishnendu Chakrabarty
2019Fault-Tolerant Neuromorphic Computing Systems.
Arjun Chaudhuri, Mengyun Liu, Krishnendu Chakrabarty
2019Hardware Fault Tolerance for Binary RRAM Crossbars.
Arjun Chaudhuri, Bonan Yan, Yiran Chen, Krishnendu Chakrabarty
2019High Quality Test Methodology for Highly Reliable Devices.
Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang
2019IEEE European Test Symposium (ETS).
Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu
2019IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR).
Szilárd Enyedi, Liviu Miclea
2019IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future.
Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor
2019IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019
2019IEEE Std. P1687.1: Translator and Protocol.
Erik Larsson, Prathamesh Murali, Gani Kumisbek
2019Improving Test Chip Design Efficiency via Machine Learning.
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
2019International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia.
Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
2019Is Backside the New Backdoor in Modern SoCs?: Invited Paper.
Nidish Vashistha, M. Tanjidur Rahman, Olivia P. Paradis, Navid Asadizanjani
2019Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults.
Irith Pomeranz
2019Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation.
Mengyun Liu, Xin Li, Krishnendu Chakrabarty, Xinli Gu
2019Machine Learning-Based Automatic Generation of eFuse Configuration in NAND Flash Chip.
Jisuk Kim, Jinyub Lee, Sungjoo Yoo
2019Machine Learning-Based DFT Recommendation System for ATPG QOR.
Apik Zorian, Basim Shanyour, Milir Vaseekar
2019Memory FIT Rate Mitigation Technique for Automotive SoCs.
Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2019Methodology of Generating Timing-Slack-Based Cell-Aware Tests.
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2019Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic.
Fangzhou Wang, Sandeep Gupta
2019On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach.
Fei Su, Prashant Goteti, Min Zhang
2019Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications.
Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula
2019Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration.
Wei Chu, Shi-Yu Huang
2019Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips.
Tung-Che Liang, Krishnendu Chakrabarty, Ramesh Karri
2019Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation.
Sreeja Chowdhury, Fatemeh Ganji, Troy Bryant, Nima Maghari, Domenic Forte
2019Reliability Modeling and Mitigation for Embedded Memories.
Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui
2019Resiliency of automotive object detection networks on GPU architectures.
Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang
2019Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction.
Zheng Xu, Jacob Abraham
2019Security Compliance Analysis of Reconfigurable Scan Networks.
Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2019Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL.
Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov
2019SoC Security Verification using Property Checking.
Nusrat Farzana, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi
2019Structural Test and Functional Test for Digital Acoustofluidic Biochips.
Zhanwei Zhong, Haodong Zhu, Peiran Zhang, Tony Jun Huang, Krishnendu Chakrabarty
2019Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion.
Kosuke Ikeda, Keith Schaub, Ira Leventhal, Yiorgos Makris, Constantinos Xanthopoulos, Deepika Neethirajan
2019Test Time and Area Optimized BrST Scheme for Automotive ICs.
Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
2019TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning.
Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee
2019Testing Computation-in-Memory Architectures Based on Emerging Memories.
Said Hamdioui, Moritz Fieback, Surya Nagarajan, Mottaqiallah Taouil
2019Testing of Neuromorphic Circuits: Structural vs Functional.
Anteneh Gebregiorgis, Mehdi Baradaran Tahoori
2019The Challenges of Implementing an MBIST Interface: A Practical Application.
Teresa McLaurin, Rob Knoth
2019Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution.
Yi He, Yanjing Li
2019Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques.
Stephan Eggersglüß
2019VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration.
Gaurav Rajavendra Reddy, Mohammad-Mahdi Bidmeshki, Yiorgos Makris
2019Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.
Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
2019Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs.
Tal Kogan, Yehonatan Abotbol