ITC A

95 papers

YearTitle / Authors
20142014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014
2014A Tag based solution for efficient utilization of efuse for memory repair.
Harsharaj Ellur, Kalpesh Shah
2014A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers.
Myeong-Jae Park, Jaeha Kim
2014A diagnosis-friendly LBIST architecture with property checking.
Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao
2014A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs.
Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow
2014A novel RF self test for a combo SoC on digital ATE with multi-site applications.
Chun-Hsien Peng, ChiaYu Yang, Adonis Tsu, Chung-Jin Tsai, Yosen Chen, C.-Y. Lin, Kai Hong, Kaipon Kao, Paul C. P. Liang, Chao Long Tsai, Charles Chien, H. C. Hwang
2014A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time.
Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang
2014A self-tuning architecture for buck converters based on alternative test.
Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee
2014A tale of two lives: Under test and in the wild.
Bianca Schroeder
2014A test probe for TSV using resonant inductive coupling.
Rashid Rashidzadeh, Iftekhar Ibne Basith
2014ATE and test equipment vendors; Hardware not software.
Mark Roos
2014Achieving extreme scan compression for SoC Designs.
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane
2014An efficient diagnosis-aware pattern generation procedure for transition faults.
Kuen-Jong Lee, Cheng-Hung Wu
2014Analog fault models: Back to the future?
Mani Soma
2014Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs.
Luca Cassano
2014Analytical MRAM test.
Raphael Robertazzi, Janusz Nowak, Jonathan Sun
2014At-speed capture power reduction using layout-aware granular clock gate enable controls.
Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi
2014Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.
Shanghang Zhang, Xin Li, Ronald D. Blanton, José Machado da Silva, John M. Carulli Jr., Kenneth M. Butler
2014Big data and test.
Anne Gattiker
2014Board manufacturing test correlation to IC manufacturing test.
C. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy
2014Board security enhancement using new locking SIB-based architectures.
Jennifer Dworak, Zoe Conroy, Alfred L. Crouch, John C. Potter
2014Challenges of testing 100M chips.
Sajjad Pagarkar
2014Clustering-based failure triage for RTL regression debugging.
Zissis Poulos, Andreas G. Veneris
2014Collaboration and teamwork obstacles.
Wesley Smith
2014Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns.
Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick
2014Compositional verification using formal analysis for a flight critical system.
Guillaume Brat
2014Concerns over predictability of supply and quality.
Carl Bowen
2014Counterfeit IC detection using light emission.
Peilin Song, Franco Stellari, Alan J. Weger
2014Delivering security by design in the Internet of Things.
Bill Curtis
2014Design and test of analog circuits towards sub-ppm level.
Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen
2014Design, technology and yield in the post-moore era.
Greg Yeric
2014Design, test & repair methodology for FinFET-based memories.
Yervant Zorian
2014DfST: Design for secure testability.
Samah Mohamed Saeed
2014Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.
Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui
2014Divide and conquer diagnosis for multiple defects.
Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li
2014Dynamic microgrids - A potential solution for enhanced resiliency in distribution systems.
Mani Vadari
2014EAGLE: A regression model for fault coverage estimation using a simulation based metric.
Shahrzad Mirkhani, Jacob A. Abraham
2014Efficient RAS support for die-stacked DRAM.
Hyeran Jeon, Gabriel H. Loh, Murali Annavaram
2014Efficient SAT-based ATPG techniques for all multiple stuck-at faults.
Masahiro Fujita, Alan Mishchenko
2014Efficient testing of hierarchical core-based SOCs.
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2014Emulation and its connection to test.
Kenneth Larsen
2014Energy-secure computer architectures.
Pradip Bose
2014Error prediction and detection methodologies for reliable circuit operation under NBTI.
Julio Vazquez Hernandez
2014FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects.
Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich
2014Fast BIST of I/O Pin AC specifications and inter-chip delays.
Stephen Sunter, Saghir A. Shaikh, Qing Lin
2014Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped data.
Li Xu, Degang Chen
2014Fault sharing in a copy-on-write based ATPG system.
X. Cai, Peter Wohl, Daniel Martin
2014Feature engineering with canonical analysis for effective statistical tests screening test escapes.
Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng
2014IC laser trimming speed-up through wafer-level spatial correlation modeling.
Constantinos Xanthopoulos, Ke Huang, Abbas Poonawala, Amit Nahar, Bob Orr, John M. Carulli Jr., Yiorgos Makris
2014Improving test compression with scan feedforward techniques.
Sreenivaas S. Muthyala, Nur A. Touba
2014Interposer test: Testing PCBs that have shrunk 100x.
T. M. Mak
2014Intra-die process variation aware anomaly detection in FPGAs.
Youngok K. Pino, Vinayaka Jyothi, Matthew French
2014Isometric test compression with low toggling activity.
Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014Knowledge discovery and knowledge transfer in board-level functional fault diagnosis.
Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu
2014Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screening.
Andreas Kux, Rudolf Ullmann, Thomas Kern, Roland Strunz, Hanno Melzner, Stephan Beuven, Andreas Haase
2014Logic characterization vehicle design for maximal information extraction for yield learning.
Ronald D. Blanton, Ben Niewenhuis, Carl Taylor
2014Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals.
Nicholas Tzou, Debesh Bhatta, Abhijit Chatterjee
2014Low-cost phase noise testing of complex RF ICs using standard digital ATE.
Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre
2014Low-distortion signal generation for ADC testing.
Fumitaka Abe, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, Haruo Kobayashi
2014Managing signal, power and thermal integrity for 3D integration.
Madhavan Swaminathan
2014Market opportunities and testing challenges for millimeter-wave radios and radars.
Brian A. Floyd
2014Massive signal tracing using on-chip DRAM for in-system silicon debug.
Sergej Deutsch, Krishnendu Chakrabarty
2014Microgrids as a resiliency resource.
Kevin Schneider
2014Mitigating voltage droop during scan with variable shift frequency.
John Schulze, Ryan Tally
2014On the testing of hazard activated open defects.
Chao Han, Adit D. Singh
2014On-chip constrained random stimuli generation for post-silicon validation using compact masks.
Xiaobing Shi, Nicola Nicolici
2014Optimizing redundancy design for chip-multiprocessors for flexible utility functions.
Da Cheng, Sandeep K. Gupta
2014Practical random sampling of potential defects for analog fault simulation.
Stephen Sunter, Krzysztof Jurga, Peter Dingenen, Ronny Vanhooren
2014Process defect trends and strategic test gaps.
Paul G. Ryan, Irfan Aziz, William B. Howell, Teresa K. Janczak, Davia J. Lu
2014Protecting against emerging vmin failures in advanced technology nodes.
J. K. Jerry Lee, Amr Haggag, William Eklow
2014Read disturb fault detection in STT-MRAM.
Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori
2014Recruiting distributed resources for grid resilience: The need for transparency.
Alexandra von Meier
2014Redundancy architectures for channel-based 3D DRAM yield improvement.
Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2014Robustness of TAP-based scan networks.
Farrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson
2014Security solutions in the first-generation Zynq All-Programmable SoC.
Steve Trimberger
2014Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation.
Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam
2014Software in a hardware view: New models for HW-dependent software in SoC verification and test.
Carlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz
2014Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris
2014Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills.
Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
2014Systematic approach for trim test time optimization: Case study on a multi-core RF SOC.
Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji
2014Teaching an old dog new tricks: Views on the future of mixed-signal IC design.
Boris Murmann
2014Test pattern generation in presence of unknown values based on restricted symbolic logic.
Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2014Test-mode-only scan attack and countermeasure for contemporary scan architectures.
Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
2014Testing silicon TV tuners on ATE without TV signal generator.
Y. Fan, A. Verma, J. Janney, S. Kumar
2014The case for analyzing system level failures using structural patterns.
Harry H. Chen
2014The desire-friction ratio of Adaptive test.
Stacy Ajouri
2014The importance of DFX, a foundry perspective.
Saman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh
2014Thermal-aware mobile SoC design and test in 14nm finfet technology.
Bong Hyun Lee
2014Top ten challenges in Big Data security and privacy.
Praveen K. Murthy
2014Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors.
Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
2014Vesuvius-3D: A 3D-DfT demonstrator.
Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr
2014Wafer Level Chip Scale Package copper pillar probing.
Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2014Welcome message.
Michael Purtell, Subhasish Mitra
2014Yield and performance improvement through technology-design co-optimization in advanced technology nodes.
Yue Liang
2014Yield optimization using advanced statistical correlation methods.
Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir