| 2011 | 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011 Bill Eklow, R. D. (Shawn) Blanton |
| 2011 | A Software-Based Self-Test methodology for on-line testing of processor caches. George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos |
| 2011 | A fully cell-based design for timing measurement of memory. Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao |
| 2011 | A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab |
| 2011 | A novel robust and accurate spectral testing method for non-coherent sampling. Siva Sudani, Minshun Wu, Degang Chen |
| 2011 | A novel scan segmentation design method for avoiding shift timing failure in scan testing. Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang |
| 2011 | A systems perspective on the R&D of industrial technology. Jyuo-Min Shyu |
| 2011 | Accurate signature driven power conscious tuning of RF systems using hierarchical performance models. Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee |
| 2011 | Actual implementation of multi domain test: Further reduction of cost of test. Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura |
| 2011 | Adaptive multidimensional outlier analysis for analog and mixed signal circuits. Ender Yilmaz, Sule Ozev, Kenneth M. Butler |
| 2011 | Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. Stephen K. Sunter, Aubin Roy |
| 2011 | Analyzing ATE interconnect performance for serial links of 10 Gbps and above. Mitchell Lin, Tyler Tolman |
| 2011 | Application of a continuous-time level crossing quantization method for timing noise measurements. Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu |
| 2011 | Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson |
| 2011 | Cell-aware analysis for small-delay effects and production test results from different fault models. Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers |
| 2011 | Challenges and best practices in advanced silicon debug. Jing Zeng |
| 2011 | Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen |
| 2011 | DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji |
| 2011 | Defect Oriented Testing for analog/mixed-signal devices. Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing |
| 2011 | Design-for-debug layout adjustment for FIB probing and circuit editing. Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen |
| 2011 | Deterministic IDDQ diagnosis using a net activation based model. Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng |
| 2011 | Development of an ATE test cell for at-speed characterization and production testing. Jose Moreira |
| 2011 | Die-level adaptive test: Real-time test reordering and elimination. Kapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar |
| 2011 | EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2011 | Efficient combination of trace and scan signals for post silicon validation and debug. Kanad Basu, Prabhat Mishra, Priyadarsan Patra |
| 2011 | Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal. Hideo Okawara |
| 2011 | End-to-end error correction and online diagnosis for on-chip networks. Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng |
| 2011 | Evaluation of TSV and micro-bump probing for wide I/O testing. Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel |
| 2011 | Faster-than-at-speed test for increased test quality and in-field reliability. Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara |
| 2011 | Forward prediction based on wafer sort data - A case study. Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir |
| 2011 | Generic, orthogonal and low-cost March Element based memory BIST. Ad J. van de Goor, Said Hamdioui, Halil Kukner |
| 2011 | Hardware hooks for transition scan characterization. Pankaj Pant, Eric Skeels |
| 2011 | IEEE Std 1581 - A standardized test access methodology for memory devices. Heiko Ehrenberg, Bob Russell |
| 2011 | In circuit test (ICT): The king is dead; long live the king! Bailarico Balangue |
| 2011 | Industry leaders panel - How will testing change in the next 10 years? Phil Nigh |
| 2011 | Investigation into voltage and process variation-aware manufacturing test. Urban Ingelsson, Bashir M. Al-Hashimi |
| 2011 | Lithography aware critical area estimation and yield analysis. Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu |
| 2011 | Logic BIST silicon debug and volume diagnosis methodology. M. Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan |
| 2011 | Low power compression utilizing clock-gating. Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy |
| 2011 | Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. A. M. Majid, David C. Keezer |
| 2011 | Multi-site test of RF transceivers on low-cost digital ATE. Ivo Koren, Ben Schuffenhauer, Frank Demmerle, Frank Neugebauer, Gert Pfahl, Dirk Rautmann |
| 2011 | On using address scrambling to implement defect tolerance in SRAMs. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2011 | Online timing variation tolerance for digital integrated circuits. Guihai Yan, Xiaowei Li |
| 2011 | Optimal manufacturing flow to determine minumum operating voltage. Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas |
| 2011 | P-PET: Partial pseudo-exhaustive test for high defect coverage. Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich |
| 2011 | Partial state monitoring for fault detection estimation. Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak |
| 2011 | Physically-aware analysis of systematic defects in integrated circuits. Wing Chiu Tam, R. D. (Shawn) Blanton |
| 2011 | Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | Power, programmability, and granularity: The challenges of ExaScale computing. Bill Dally |
| 2011 | Pre-bond probing of TSVs in 3D stacked ICs. Brandon Noia, Krishnendu Chakrabarty |
| 2011 | Real-time testing method for 16 Gbps 4-PAM signal interface. Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu |
| 2011 | Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks. Zhaobo Zhang, Krishnendu Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu |
| 2011 | State of the art low capture power methodology. Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto |
| 2011 | Surviving state disruptions caused by test: A case study. Kenneth P. Parker, Shuichi Kameyama, David Dubberke |
| 2011 | Techniques to improve memory interface test quality for complex SoCs. V. R. Devanathan, Srinivas Kumar Vooka |
| 2011 | Test access and the testability features of the Poulson multi-core Intel Itanium® processor. Dilip K. Bhavsar, Steve Poehlman |
| 2011 | Test clock domain optimization for peak power supply noise reduction during scan. Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li |
| 2011 | Test cost reduction through performance prediction using virtual probe. Hsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler |
| 2011 | The gap: Test challenges in Asia manufacturing field. Xinli Gu |
| 2011 | Transition test bring-up and diagnosis on UltraSPARC Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson |
| 2011 | Using well/substrate bias manipulation to enhance voltage-test-based defect detection. Anne E. Gattiker, Phil Nigh |
| 2011 | Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study. Dragoljub Gagi Drmanac, Michael Laisne |