| 2010 | 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010 Ron Press, Erik H. Volkerink |
| 2010 | A MEMS based device interface board. Nabeeh Kandalaft, Iftekhar Ibne Basith, Rashid Rashidzadeh |
| 2010 | A diagnostic test generation system. Yu Zhang, Vishwani D. Agrawal |
| 2010 | A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam |
| 2010 | A high density small size RF test module for high throughput multiple resource testing. Masayuki Kimishima, S. Mizuno, T. Seki, H. Takeuti, Haruki Nagami, Hideki Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi |
| 2010 | A high linearity compact timing vernier for CMOS timing generator. Jun Kohno, Tatsuro Akiyama, Dai Kato, Makoto Imamura |
| 2010 | A kernel-based approach for functional test program generation. Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra |
| 2010 | A low-cost ATE phase signal generation technique for test applications. Sadok Aouini, Kun Chuai, Gordon W. Roberts |
| 2010 | A new method for estimating spectral performance of ADC from INL. Jingbo Duan, Le Jin, Degang Chen |
| 2010 | A novel approach to improve test coverage of BSR cells. Ankush Srivastava, Ajay Prajapati, Vinay Soni |
| 2010 | A practical scan re-use scheme for system test. Kelly Lee |
| 2010 | A programmable BIST for DRAM testing and diagnosis. Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Y. Zhang |
| 2010 | A roaming memory test bench for detecting particle induced SEUs. Jean-Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo |
| 2010 | A tester architecture suitable for MEMS calibration and testing. Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Maurizio Straiotto, Luciano Bonaria |
| 2010 | ADC linearity testing method with single analog monitoring port. Tomohiro Kawachi, Koichi Irie |
| 2010 | AXIe® 2.0 and MVP-C: Open ATE software standards. Kenneth Spargo |
| 2010 | AXIe®: Open architecture test system standard. Al Czamara |
| 2010 | Adaptive test flow for mixed-signal/RF circuits using learned information from device under test. Ender Yilmaz, Sule Ozev, Kenneth M. Butler |
| 2010 | An on-line monitoring technique for electrode degradation in bio-fluidic microsystems. Qais Al-Gayem, Hongyuan Liu, Andrew Richardson, Nick Burd, M. Kumar |
| 2010 | Analog neural network design for RF built-in self-test. Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris |
| 2010 | Automated test program generation for automotive devices. Anke Drappa, Peter Huber, Jon Vollmar |
| 2010 | Automated trace signals selection using the RTL descriptions. Ho Fai Ko, Nicola Nicolici |
| 2010 | Automatic classification of bridge defects. Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton |
| 2010 | BIST of I/O circuit parameters via standard boundary scan. Stephen K. Sunter, Matthias Tilmann |
| 2010 | Board-level fault diagnosis using an error-flow dictionary. Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty |
| 2010 | Case study of scan chain diagnosis and PFA on a low yield wafer. Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen |
| 2010 | Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test. Rosa D. Reinosa, Aileen Allen, Elizabeth Benedetto, Alan Mcallister |
| 2010 | Clock Gate Test Points. Narendra Devta-Prasanna, Arun Gunda |
| 2010 | Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab |
| 2010 | Commanded Test Access Port operations. Lee Whetsel |
| 2010 | Complete testing of receiver jitter tolerance. Timothy D. Lyons |
| 2010 | Concurrent test planning. Bethany Van Wagenen, Edward Seng |
| 2010 | Constrained ATPG for functional RTL circuits using F-Scan. Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2010 | DFM aware bridge pair extraction for manufacturing test development. Sarveswara Tammali, Vishal Khatri, Gowrysankar Shanmugam, Mark Terry |
| 2010 | Defect-oriented cell-internal testing. Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger |
| 2010 | Design and test of latch-based circuits to maximize performance, yield, and delay test quality. Kun Young Chung, Sandeep K. Gupta |
| 2010 | Detecting and diagnosing open defects. Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson |
| 2010 | Detecting memory faults in the presence of bit line coupling in SRAM devices. Sandra Irobi, Zaid Al-Ars, Said Hamdioui |
| 2010 | Dynamic channel allocation for higher EDT compression in SoC designs. Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer |
| 2010 | Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. Saeed Shamshiri, Kwang-Ting Cheng |
| 2010 | Estimating defect-type distributions through volume diagnosis and defect behavior attribution. Xiaochun Yu, Ronald D. Blanton |
| 2010 | Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers. Koji Asami, Toshiaki Kurihara, Yushi Inada |
| 2010 | Experiences with parametric BIST for production testing PLLs with picosecond precision. Rakesh Kinger, Swetha Narasimhawsamy, Stephen K. Sunter |
| 2010 | Fault models and test methods for subthreshold SRAMs. Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang |
| 2010 | Hard to find, easy to find systematics; just find them. Rao Desineni, Leah Pastel, Maroun Kassab, Robert Redburn |
| 2010 | Highly efficient parallel ATPG based on shared memory. X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath |
| 2010 | Improving fault diagnosis accuracy by automatic test set modification. Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso |
| 2010 | Increasing PRPG-based compression by delayed justification. Peter Wohl, John A. Waicukauski, T. Finklea |
| 2010 | Is test power reduction through X-filling good enough? Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed |
| 2010 | Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash |
| 2010 | Leveraging existing power control circuits and power delivery architecture for variability measurement. Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic |
| 2010 | Low capture power at-speed test in EDT environment. Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab |
| 2010 | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2010 | Low power compression of incompatible test cubes. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer |
| 2010 | MT-SBST: Self-test optimization in multithreaded multicore architectures. Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González |
| 2010 | Mask versus Schematic - an enhanced design-verification flow for first silicon success. Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang |
| 2010 | Methodology for early and accurate test power estimation at RTL. Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe |
| 2010 | Mining AC delay measurements for understanding speed-limiting paths. Janine Chen, Brendon Bolin, Li-C. Wang, Jing Zeng, Dragoljub Gagi Drmanac, Michael Mateja |
| 2010 | Modeling TSV open defects in 3D-stacked DRAM. Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu |
| 2010 | Modeling the impact of process variation on resistive bridge defects. S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu |
| 2010 | Multiple fault activation cycle tests for transistor stuck-open faults. Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz |
| 2010 | Mutation-based diagnostic test generation for hardware design error diagnosis. Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong |
| 2010 | New tools and methodology for advanced parametric and defect structure test. Raphael Robertazzi, Louis Medina, Ernesto Shiling, Garry Moore, Ronald Geiger, Jiun-Hsin Liao, John Williamson |
| 2010 | On generation of a universal path candidate set containing testable long paths. Zijian He, Tao Lv, Huawei Li, Xiaowei Li |
| 2010 | On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen |
| 2010 | On techniques for handling soft errors in digital circuits. Warin Sootkaneung, Kewal K. Saluja |
| 2010 | Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2010 | Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration. Minki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay |
| 2010 | Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages. Ki-Jae Song, Hunkyo Seo, Sang-hyun Ko |
| 2010 | Parity prediction synthesis for nano-electronic gate designs. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2010 | Path coverage based functional test generation for processor marginality validation. Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche |
| 2010 | Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. Rudrajit Datta, Nur A. Touba |
| 2010 | Post-production performance calibration in analog/RF devices. Nathan Kupp, He Huang, Petros Drineas, Yiorgos Makris |
| 2010 | Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs. Suri Basharapandiyan, Yi Cai |
| 2010 | Precision audio nulling instrumentation achieves near -140dB measurements in a production environment. Carl Karandjeff, Chris Hannaford |
| 2010 | Predictive analysis for projecting test compression levels. Ozgur Sinanoglu, Sobeeh Almukhaizim |
| 2010 | Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing. Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird |
| 2010 | QED: Quick Error Detection tests for effective post-silicon validation. Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, Subhasish Mitra |
| 2010 | RADPro: Automatic RF analyzer and diagnostic program generation tool. Sukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzlar, Richard Antley, Craig Force, Falah Mohammed |
| 2010 | RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara |
| 2010 | Rapid FPGA delay characterization using clock synthesis and sparse sampling. Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar |
| 2010 | Redundant core testing on the cell BE microprocessor. David Iverson, Dan Dickinson, John Masson, Christina Newman-LaBounty, Daniel Simmons, William Tanona |
| 2010 | STIL P1450.4: A standard for test flow specification. Jim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas |
| 2010 | Scan chain securization though Open-Circuit Deadlocks. Michele Portolan, Bradford G. Van Treuren, Suresh Goyal |
| 2010 | Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. Rance Rodrigues, Sandip Kundu, Omer Khan |
| 2010 | Soft error reliability aware placement and routing for FPGAs. Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori |
| 2010 | Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins. C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill |
| 2010 | Structural approach for built-in tests in RF devices. Deepa Mannath, Dallas Webster, Victor Montaño-Martinez, David Cohen, Shai Kush, Ganesan Thiagarajan, Adesh Sontakke |
| 2010 | Surviving state disruptions caused by test: The "Lobotomy Problem". Kenneth P. Parker |
| 2010 | Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude. Devin Morris, William R. Eisenstadt, Andrea Paganini, Mustapha Slamani, Timothy Platt, John Ferrario |
| 2010 | System reliability evaluation using concurrent multi-level simulation of structural faults. Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto |
| 2010 | Systematic defect identification through layout snippet clustering. Wing Chiu Tam, Osei Poku, Ronald D. Blanton |
| 2010 | Test cycle power optimization for scan-based designs. Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli |
| 2010 | Testing of latch based embedded arrays using scan tests. Fan Yang, Sreejit Chakravarty |
| 2010 | Testing the IBM Power 7™ 4 GHz eight core microprocessor. James Crafts, David Bogdan, Dennis Conti, Donato O. Forlenza, Orazio P. Forlenza, William V. Huott, Mary P. Kusko, Edward Seymour, Timothy Taylor, Brian Walsh |
| 2010 | The AB-filling methodology for power-aware at-speed scan testing. Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng |
| 2010 | The scan-DFT features of AMD's next-generation microprocessor core. Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen |
| 2010 | Timing skew compensation technique using digital filter with novel linear phase condition. Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi |
| 2010 | Towards effective and compression-friendly test of memory interface logic. V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar |
| 2010 | Using context based methods for test data compression. Sara Karamati, Zainalabedin Navabi |
| 2010 | Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran |
| 2010 | Vendor-agnostic native compression engine. Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday |
| 2010 | nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li |