ITC A

146 papers

YearTitle / Authors
2008"Plug & Test" at System Level via Testable TLM Primitives.
Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi
20082008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008
Douglas Young, Nur A. Touba
2008A Cost Analysis Framework for Multi-core Systems with Spares.
Saeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
2008A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems.
Syed Zafar Shazli, Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori, David R. Kaeli
2008A Generic Framework for Scan Capture Power Reduction in Test Compression Environment.
Xiao Liu, Feng Yuan, Qiang Xu
2008A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories.
Olivier Ginez, Jean-Michel Portal, Hassen Aziza
2008A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.
Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2008A Hybrid A/D Converter with 120dB SNR and -125dB THD.
Mamoru Tamba
2008A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.
Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang
2008A Method to Generate a Very Low Distortion, High Frequency Sine Waveform Using an AWG.
Akinori Maeda
2008A New Language Approach for IJTAG.
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing.
Takahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa
2008A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method.
Junghyun Nam, Sunghoon Chun, Gibum Koo, Yanggi Kim, Byungsoo Moon, Jonghyoung Lim, Jaehoon Joo, Sangseok Kang, Hoonjung Kim, Kyeongseon Shin, Kisang Kang, Sungho Kang
2008A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths.
Jeremy Lee, Mohammad Tehranipoor
2008A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs.
Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula
2008A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs.
Tsu-Wei Tseng, Jin-Fu Li
2008A Study of Outlier Analysis Techniques for Delay Testing.
Sean H. Wu, Dragoljub Gagi Drmanac, Li-C. Wang
2008A Tutorial on STDF Fail Datalog Standard.
Ajay Khoche, Phil Burlison, John Rowe, Glenn Plowman
2008Achieving Zero-Defects for Automotive Applications.
Rajesh Raina
2008Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors.
Ozgur Sinanoglu
2008An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements.
Kelageri Nagaraj, Sandip Kundu
2008An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis.
Xiaochun Yu, Ronald D. Blanton
2008An Efficient Secure Scan Design for an SoC Embedding AES Core.
Jaehoon Song, Taejin Jung, Junseop Lee, Hyeran Jeong, Byeongjin Kim, Sungju Park
2008An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test.
David C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid
2008Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.
Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer
2008Architecture for Testing Multi-Voltage Domain SOC.
Laurent Souef, Christophe Eychenne, Emmanuel Alie
2008Augmenting Boundary-Scan Tests for Enhanced Defect Coverage.
Dayton Norrgard, Kenneth P. Parker
2008Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment.
Jose Moreira, Heidi Barnes, Hiroshi Kaga, Michael Comai, Bernhard Roth, Morgan Culver
2008Boundary-Scan Testing of Power/Ground Pins.
Kenneth P. Parker, Neil G. Jacobson
2008Bridging the gap between Design and Test Engineering for Functional Pattern Development.
Ernst Aderholz, Heiko Ahrens, Michael Rohleder
2008Built-in Self-Calibration of On-chip DAC and ADC.
Wei Jiang, Vishwani D. Agrawal
2008Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates.
Yang Zhao, Tao Xu, Krishnendu Chakrabarty
2008CONCAT: CONflict Driven Learning in ATPG for Industrial designs.
Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta
2008Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise.
Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng
2008Computing at the Crossroads (And What Does it Mean to Verification and Test?).
Jan M. Rabaey
2008DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG.
Heiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano
2008DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs.
Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji
2008DFX of a 3
Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar
2008Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller
2008Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.
Waleed K. Al-Assadi, Sindhu Kakarla
2008Detection and Diagnosis of Static Scan Cell Internal Defect.
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
2008Detection of Internal Stuck-open Faults in Scan Chains.
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.
Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
2008Diagnosis of Logic-to-chain Bridging Faults.
Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li
2008Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains.
Jing Ye, Fei Wang, Yu Hu, Xiaowei Li
2008Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.
Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
2008Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.
Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka
2008Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs.
Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
2008EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms.
Vishwanath Natarajan, Hyun Woo Choi, Deuk Lee, Rajarajan Senguttuvan, Abhijit Chatterjee
2008Efficient High-Speed Interface Verification and Fault Analysis.
Thomas Nirmaier, Jose Torres Zaguirre, Eric Liau, Wolfgang Spirkl, Armin Rettenberger, Doris Schmitt-Landsiedel
2008Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data.
Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann
2008Embedded Power Delivery Decoupling in Small Form Factor Test Sockets.
Omer Vikinski, Shaul Lupo, Gregory Sizikov, Chee Yee Chung
2008Embedded Testing in an In-Circuit Test Environment.
John Malian, Bill Eklow
2008Engineering Test Coverage on Complex Sockets.
Myron Schneider, Ayub Shafi
2008Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.
Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
2008External Loopback Testing Experiences with High Speed Serial Interfaces.
Anne Meixner, Akira Kakizawa, Benoit Provost, Serge Bedwani
2008Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008FPGA Time Measurement Module: Preliminary Results.
William J. Bowhers
2008Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics.
Vincent Mao, Chris Dwyer, Krishnendu Chakrabarty
2008Failing Frequency Signature Analysis.
Jaekwang Lee, Edward J. McCluskey
2008Finding Power/Ground Defects on Connectors - Case Study.
Steve Hird, Reggie Weng
2008Frequency and Power Correlation between At-Speed Scan and Functional Tests.
Shlomi Sde-Paz, Eyal Salomon
2008Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors.
Tung N. Pham, Frances Clougherty, Gerard Salem, James M. Crafts, Jon Tetzloff, Pamela Moczygemba, Timothy M. Skergan
2008Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production.
Sadok Aouini, Gordon W. Roberts
2008Hardware Overhead Reduction for Memory BIST.
Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
2008Hardware-based Error Rate Testing of Digital Baseband Communication Systems.
Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn
2008Having FUN with Analog Test.
Robert A. Pease
2008High Test Quality in Low Pin Count Applications.
Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti
2008High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST.
Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2008IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores.
Geng-Ming Chiu, James Chien-Mo Li
2008IEEE 1500 Core Wrapper Optimization Techniques and Implementation.
Brendan Mullane, Michael Higgins, Ciaran MacNamee
2008IEEE P1581 drastically simplifies connectivity test for memory devices.
Heiko Ehrenberg
2008Implementation Update: Logic Mapping On SPARC- Microprocessors.
Anjali Vij, Richard Ratliff
2008Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model.
Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas
2008Improving the Accuracy of Test Compaction through Adaptive Test Update.
Sounil Biswas, Ronald D. Blanton
2008Increasing Scan Compression by Using X-chains.
Peter Wohl, John A. Waicukauski, Frederic Neuveux
2008Integration of Hardware Assertions in Systems-on-Chip.
Jeroen Geuzebroek, Bart Vermeulen
2008Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2008Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy?
Lin Huang, Qiang Xu
2008Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps.
Mike Peng Li
2008Jitters in high performance microprocessors.
T. M. Mak
2008Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model.
Scott Davidson
2008Launch-on-Shift-Capture Transition Tests.
Intaik Park, Edward J. McCluskey
2008Leveraging IEEE 1641 for Tester-Independent ATE Software.
Bethany Van Wagenen, Jon Vollmar, Dan Thornton
2008Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter Estimation.
Le Jin
2008Low Energy On-Line SBST of Embedded Processors.
Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos
2008Low Power Scan Shift and Capture in the EDT Environment.
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008Low Power Test.
Swapnil Bahl, Rajiv Sarkar, Akhil Garg
2008Low cost testing of multi-GBit device pins with ATE assisted loopback instrument.
William Fritzsche, Asim E. Haque
2008Managing Test in the End-to-End, Mega Supply Chain.
Mike Lydon
2008Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications.
Thomas P. Warwick, Gustavo Rivera, David Waite, James Russell, Jeffrey Smith
2008Modeling Test Escape Rate as a Function of Multiple Coverages.
Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena
2008NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure.
Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi
2008Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes.
Brian Moore, Marc Mangrum, Chris Sellathamby, Md. Mahbub Reja, T. Weng, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky
2008Observations of Supply-Voltage-Noise Dispersion in Sub-nsec.
Kan Takeuchi, Genichi Tanaka, Hiroaki Matsushita, Kenichi Yoshizumi, Yusaku Katsuki, Takao Sato
2008Octal-Site EVM Tests for WLAN Transceivers on "Very" Low-Cost ATE Platforms.
Ganesh Srinivasan, Hui-Chuan Chao, Friedrich Taenzler
2008On Accelerating Path Delay Fault Simulation of Long Test Sequences.
I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta
2008On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.
Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris
2008On-chip Programmable Capture for Accurate Path Delay Test and Characterization.
Rajeshwary Tayade, Jacob A. Abraham
2008On-chip Timing Uncertainty Measurements on IBM Microprocessors.
Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem
2008On-line Failure Detection in Memory Order Buffers.
Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella
2008Optical Diagnostics for IBM POWER6- Microprocessor.
Peilin Song, Stephen Ippolito, Franco Stellari, John Sylvestri, Tim Diemoz, George Smith, Paul Muench, Norm James, Seongwon Kim, Hector Saenz
2008Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra
2008Optimized EVM Testing for IEEE 802.11a/n RF ICs.
Erkan Acar, Sule Ozev, Ganesh Srinivasan, Friedrich Taenzler
2008Overview of IEEE P1450.6.2 Standard; Creating CTL Model For Memory Test and Repair.
2008Overview of a High Speed Top Side Socket Solution.
John Stewart, Temitope Animashaun
2008Parametric Testing of Optical Interfaces.
Brice Achkir, Pavel Zivny, Bill Eklow
2008Peak Power Reduction Through Dynamic Partitioning of Scan Chains.
Sobeeh Almukhaizim, Ozgur Sinanoglu
2008Platform Independent Test Access Port Architecture.
Arie Margulis, David Akselrod, Tim Wood, Sopho Metsis
2008Power Distribution Failure Analysis Using Transition-Delay Fault Patterns.
Junxia Ma, Jeremy Lee, Mohammad Tehranipoor
2008Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks.
Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote
2008Problems Using Boundary-Scan for Memory Cluster Tests.
Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker
2008Production Multivariate Outlier Detection Using Principal Components.
Peter M. O'Neill
2008RTL Error Diagnosis Using a Word-Level SAT-Solver.
Saeed Mirzaeian, Feijun (Frank) Zheng, Kwang-Ting (Tim) Cheng
2008Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.
Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
2008Robust Design-for-Productization Practices for High Quality Automotive Products.
Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello
2008SAT-based State Justification with Adaptive Mining of Invariants.
Weixin Wu, Michael S. Hsiao
2008SOC Test Optimization with Compression-Technique Selection.
Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty
2008Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects.
Adit D. Singh
2008SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects.
Feng Yuan, Qiang Xu
2008SoC Yield Improvement: Redundant Architectures to the Rescue?
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008Solder Bead on High Density Interconnect Printed Circuit Board.
Brandon Chu
2008Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application.
Dave F. Dubberke, James J. Grealish, Bill Van Dick
2008Statistical Yield Modeling for Sub-wavelength Lithography.
Aswin Sreedhar, Sandip Kundu
2008System JTAG Initiative Group Advancements.
Bradford G. Van Treuren
2008Test Access Mechanism for Multiple Identical Cores.
Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield
2008Test Generation for Interconnect Opens.
Xijiang Lin, Janusz Rajski
2008Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study.
Che-Jen Jerry Chang, Takeo Kobayashi
2008Test-Access Solutions for Three-Dimensional SOCs.
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
2008Testing Methodology of Embedded DRAMs.
Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen
2008Testing Techniques for Hardware Security.
Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak
2008The Advantages of Limiting P1687 to a Restricted Subset.
Jason Doege, Alfred L. Crouch
2008The Economics of Harm Prevention through Design for Testability.
Louis Y. Ungar
2008The Importance of Functional-Like Access for Memory Test.
Jonathan Phelps, Chuck Johnson, Corey Goodrich, Aman Kokrady
2008The Test Features of the Quad-Core AMD Opteron- Microprocessor.
Tim Wood, Grady Giles, Chris Kiszely, Martin Schuessler, Daniela Toneva, Joel Irby, Michael Mateja
2008This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company.
Jeff Rearick
2008Time-dependent Behaviour of Full Open Defects in Interconnect Lines.
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2008Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality.
Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi
2008Transition Test on UltraSPARC- T2 Microprocessor.
Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen
2008Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008Unraveling Variability for Process/Product Improvement.
Anne Gattiker
2008Using Implications for Online Error Detection.
Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
2008VAST: Virtualization-Assisted Concurrent Autonomous Self-Test.
Hiroaki Inoue, Yanjing Li, Subhasish Mitra
2008VLSI Test Exercise Courses for Students in EE Department.
Satoshi Komatsu
2008Wafer-Level Characterization of Probecards using NAC Probing.
Gyu-Yeol Kim, Eon-Jo Byunb, Ki-Sang Kang, Young-Hyun Jun, Bai-Sun Kong
2008Wireless Test Structure for Integrated Systems.
Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard