ITC A

119 papers

YearTitle / Authors
20062006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006
Scott Davidson, Anne Gattiker
2006A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing.
Jeff Rearick, Aaron Volz
2006A Framework of High-quality Transition Fault ATPG for Scan Circuits.
Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.
Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz
2006A High Speed Reduced Pin Count JTAG Interface.
Lee Whetsel
2006A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior.
Rao Desineni, Osei Poku, Ronald D. Blanton
2006A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2006A Novel Ganged DAC Solution for Multi-Site Testing.
Joseph Kwan, Qing Zhao
2006A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.
Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu
2006A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE.
Sadok Aouini, Gordon W. Roberts
2006A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis.
Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware
2006A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement.
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
2006A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen
2006A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise.
Erdem Serkan Erdogan, Sule Ozev
2006A Study of Implication Based Pseudo Functional Testing.
Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty
2006A Study of Per-Pin Timing Jitter Scope.
Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma
2006A Survey of Test Problems and Solutions.
Jeff Rearick
2006A Unified Approach to Test Generation and Test Data Volume Reduction.
Yung-Chieh Lin, Kwang-Ting Cheng
2006Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation.
Selim Sermet Akbay, Jose L. Torres, Julie M. Rumer, Abhijit Chatterjee, Joel Amtsfield
2006An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA.
Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar
2006An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space.
Leonard Lee, Li-C. Wang
2006An Enhanced EDAC Methodology for Low Power PSRAM.
Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin
2006Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test.
Bambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg
2006At-Speed Structural Test For High-Performance ASICs.
Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich
2006Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor.
Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham
2006BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.
Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
2006Behavioral Test Economics.
Scott Davidson, Anthony P. Ambler, Helen Davidson
2006Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links.
Dongwoo Hong, Kwang-Ting Cheng
2006Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method.
Hongjoong Shin, Joonsung Park, Jacob A. Abraham
2006Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues.
Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins
2006Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation.
Xiaoding Chen, Michael S. Hsiao
2006Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks.
Zahi S. Abuhamdeh, Philip Pears, Jeff Remmers, Alfred L. Crouch, Bob Hannagan
2006Classifying Bad Chips and Ordering Test Sets.
François-Fabien Ferhani, Edward J. McCluskey
2006Combinational Logic Soft Error Correction.
Subhasish Mitra, Ming Zhang, Saad Waqas, Norbert Seifert, Balkaran S. Gill, Kee Sup Kim
2006Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing.
Sofiane Ellouz, Patrice Gamand, Christophe Kelma, Bertrand Vandewiele, Bruno Allard
2006Comparison of Delay Tests on Silicon.
Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore
2006Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICs.
Liquan Fang, Mohammed Lemnawar, Yizi Xing
2006Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.
Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng
2006DIBPro: Automatic Diagnostic Program Generation Tool.
Venkat Kalyanaraman, Bruce C. Kim, Pramodchandran N. Variyam, Sasikumar Cherubal
2006DRAM-Specific Space of Memory Tests.
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath
2006Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment.
Anne Gattiker, Manjul Bhushan, Mark B. Ketchen
2006Debug of the CELL Processor: Moving the Lab into Silicon.
Mack W. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura
2006Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs.
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2006Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk.
Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota
2006Design for Board and System Level Structural Test and Diagnosis.
Toai Vo, Zhiyuan Wang, Ted Eaton, Pradipta Ghosh, Huai Li, Young Lee, Weili Wang, Hong Shin Jun, Rong Fang, Dan Singletary, Xinli Gu
2006Diagnosis with Limited Failure Information.
Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
2006Diagnostic Test Generation for Arbitrary Faults.
Naresh K. Bhatti, Ronald D. Blanton
2006Efficient Latch and Clock Structures for System-on-Chip Test Flexibility.
David E. Lackey
2006Embedded Memory Diagnosis: An Industrial Workflow.
Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2006Embedded Memory Field Returns - Trials and Tribulations.
Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas
2006Estimating Error Rate during Self-Test via One's Counting.
Shideh Shahidi, Sandeep K. Gupta
2006Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits.
Chong Zhao, Sujit Dey
2006Exact At-speed Delay Fault Grading in Sequential Circuits.
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
2006Fault Coverage Estimation for Non-Random Functional Input Sequences.
Soumitra Bose, Vishwani D. Agrawal
2006Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences.
Irith Pomeranz, Sudhakar M. Reddy
2006Fault Modeling and Detection for Drowsy SRAM Caches.
Wei Pei, Wen-Ben Jone, Yiming Hu
2006Fully automated semiconductor operating condition testing.
Thomas Nirmaier, Wolfgang Spirkl, Eric Liau Chee Hong
2006Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration.
Jochen Rivoir
2006HDL Program Slicing to Reduce Bounded Model Checking Search Overhead.
Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham
2006High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission Images.
Franco Stellari, Peilin Song, Tim Diemoz, Alan J. Weger, Tami Vogel, Steven C. Wilson, John Pennings, Richard F. Rizzolo
2006IEEE P1581 - Getting More Board Test Out of Boundary Scan.
Heiko Ehrenberg
2006IEEE P1687: Toward Standardized Access of Embedded Instrumentation.
Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote
2006ISI Injection Filter Designs Using PIN and Varactor Diodes for SerDes Testing on ATE.
Fengming Zhang, Warren Necoechea
2006Implementation of Solder-bead Probing in High Volume Manufacturing.
Madhavan Doraiswamy, James J. Grealish
2006Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories.
Rahul Nadkarni, Igor Arsovski, Reid Wistort, Valerie Chickanosky
2006Improving Precision Using Mixed-level Fault Diagnosis.
M. Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman
2006Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.
Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich
2006Integrated RF-CMOS Transceivers challenge RF Test.
Frank Demmerle
2006Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains.
Hyunbean Yi, Jaehoon Song, Sungju Park
2006Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective.
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
2006Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis.
Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li
2006Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit Test.
Rosa D. Reinosa
2006Linearity Test of Analog-to-Digital Converters Using Kalman Filtering.
Le Jin, Degang Chen, Randall L. Geiger
2006Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules.
Mohamed Hafed, Daniel Watkins, Clarence Tam, Bardia Pishdad
2006Modeling and Testing Process Variation in Nanometer CMOS.
Mehrdad Nourani, Arun Radhakrishnan
2006Multi Strobe Circuit for 2.133GHz Memory Test System.
Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka
2006Multi-Gigahertz Testing of Wafer-Level Packaged Devices.
A. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru
2006Novel Architecture for On-Chip AC Characterization of I/Os.
N. Vijayaraghavan, Balwant Singh, Saurabh Singh, Vishal Srivastava
2006OCI: Open Compression Interface.
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
2006On-chip Test and Repair of Memories for Static and Dynamic Faults.
Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar
2006On-line Boundary-Scan Testing in Service of Extended Products.
Ilka Reis, Peter Collins, Marc van Houcke
2006Optimizing the Cost of Test at Intel Using per Device Data.
Robert Edmondson, Gregory Iovino, Richard Kacprowicz
2006Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing.
Eric Liau Chee Hong, Manfred Menke, Thomas Janik, Doris Schmitt-Landsiedel
2006Perfect data reconstruction algorithm of time interleaved ADCs.
Fang Xu
2006Periodic Jitter Amplitude Calibration with Walking Strobe.
Lucy Liu, Eddie Lew
2006Power Supply Noise in Delay Testing.
Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger
2006Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.
Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects.
Hiren D. Thacker, James D. Meindl
2006Recognition of Sensitized Longest Paths in Transition Delay Test.
Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato
2006Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture.
Hung-chi Lihn
2006Seamless Integration of SER in Rewiring-Based Design Space Exploration.
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
2006Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics.
Ajay Khoche, Domenico Chindamo, Michael Braun, Martin Fischer
2006Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.
Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin
2006SiP-TAP: JTAG for SiP.
Frans G. M. de Jong, Alex S. Biewenga
2006Signature Analyzer Design for Yield Learning Support.
Nishant Patil, Subhasish Mitra, Steven S. Lumetta
2006Signature Based Diagnosis for Logic BIST.
Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill
2006Structural Testing of High-Speed Serial Buses: A Case Study Analysis.
Eric Johnson
2006Structural Tests for Jitter Tolerance in SerDes Receivers.
Stephen K. Sunter, Aubin Roy
2006Technique to Detect RF Interface and Contact Issues During Production Testing.
Martin Dresler
2006Test Compression for FPGAs.
Mehdi Baradaran Tahoori, Subhasish Mitra
2006Test Data Compression of 100x for Scan-Based BIST.
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
2006Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics.
Sylvain Tourangeau, Bill Eklow
2006Test Software Generation Productivity and Code Quality Improvement by applying Software Engineering Techniques.
Stefan Vock, Markus Schmid, Hans Martin von Staudt
2006Test Structure and Testing of the Microsoft XBOX 360
Tung Pham, Brian Koehler, Daniel Young, Louis Bushard
2006Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links.
Mitchell Lin, Kwang-Ting Cheng
2006Testing MRAM for Write Disturbance Fault.
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao
2006Testing of Precision DACs Using Low-Resolution ADCs with Dithering.
Le Jin, Hosam Haggag, Randall L. Geiger, Degang Chen
2006Testing of UltraSPARC T1 Microprocessor and its Challenges.
P. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall
2006The Challenge of Testing the ARM CORTEX-A8
Teresa L. McLaurin
2006The Design and Validation of IP for DFM/DFY Assurance.
Robert C. Aitken
2006The Design, Implementation and Analysis of Test Experiments.
Peter C. Maxwell
2006The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time.
Chris Allsup
2006The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution.
Doug Heaberlin
2006The Role of ATPG Fault Diagnostics in Driving Physical Analysis.
Roger Nicholson, Cathy Kardach, Bruce Cory
2006Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology.
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006Using Limited Dependence Sequential Expansion for Decompressing Test Vectors.
Avijit Dutta, Nur A. Touba
2006Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier Detection.
Jeffrey L. Roehr
2006What is DFM & DFY and Why Should I Care ?
Rajesh Raina
2006X-Press Compactor for 1000x Reduction of Test Data.
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab