ITC A

182 papers

YearTitle / Authors
2005"Driver on a floppy" delivery of ATE instrumentation software.
Dan Proskauer
2005A 16-bit resistor string DAC with full-calibration at final test.
Kumar L. Parthasarathy, Turker Kuyel, Zhongjun Yu, Degang Chen, Randall L. Geiger
2005A DDJ calibration methodology for high-speed test and measurement equipments.
Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov
2005A comprehensive production test solution for 1.5Gb/s and 3Gb/s serial-ATA - based on AWG and undersampling techniques.
Yi Cai, Amit Bhattacharyya, Joe Martone, Anant Verma, William Burchanowski
2005A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set.
Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis, Constantin Halatsis
2005A leakage control system for thermal stability during burn-in test.
Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy
2005A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.
Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy
2005A methodology for testing one-hot transmission gate multiplexers.
Teresa L. McLaurin, Frank Frederick, Rich Slobodnik
2005A new approach for massive parallel scan design.
Woo Cheol Chung, Dong Sam Ha
2005A new probing technique for high-speed/high-density printed circuit boards.
Kenneth P. Parker
2005A novel process and hardware architecture to reduce burn-in cost.
Chris Schroeder, Jin Pan, Todd Albertson
2005A novel stuck-at based method for transistor stuck-open fault diagnosis.
Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud
2005A novel test methodology based on error-rate to support error-tolerance.
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2005A practical perspective on reducing ASIC NTFs.
Zoe Conroy, Geoff Richmond, Xinli Gu, Bill Eklow
2005A random access scans architecture to reduce hardware overhead.
Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh
2005A scalable test strategy for network-on-chip routers.
Alexandre M. Amory, Eduardo Wenzel Brião, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
2005A self-timed structural test methodology for timing anomalies due to defects and process variations.
Adit D. Singh
2005A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits.
Chong Zhao, Xiaoliang Bai, Sujit Dey
2005A strategy for board level in-system programmable built-in assisted test and built-in self test.
Joshua Ferry, Jozef Scesnak, Shoeib Shaikh
2005A structured approach for the systematic test of embedded automotive communication systems.
Eric Armengaud, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner
2005A test case for 3Gbps serial attached SCSI (SAS).
Yi Cai, Liming Fang, Robert Ratemo, J. Liu, K. Gross, Michael Kozma
2005A test point selection method for data converters using Rademacher functions and wavelet transforms.
Chandra Carter, Simon S. Ang
2005A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architectures.
Peter Collins, Ilka Reis, Mikko Simonen, Marc van Houcke
2005A vector-based approach for power supply noise analysis in test compaction.
Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2005A wideband low-noise ATE-based method for measuring jitter in GHz signals.
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma
2005Achieving higher yield through diagnosis-the ASIC perspective.
Chris Schuermyer
2005Achieving higher yield through diagnosis.
Nagesh Tamarapalli
2005Achieving higher yield through diagnosis?
Srikanth Venkataraman
2005An advanced optical diagnostic technique of IBM z990 eServer microprocessor.
Peilin Song, Franco Stellari, Bill Huott, Otto Wagner, Uma Srinivasan, Yuen H. Chan, Rick Rizzolo, H. J. Nam, James P. Eckhardt, Timothy G. McNamara, Ching-Lung Tong, Alan J. Weger, Moyra K. McManus
2005An optimal test pattern selection method to improve the defect coverage.
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
2005An update on IEEE 1149.6 - successes and issues.
Bill Eklow
2005Analysis of error-masking and X-masking probabilities for convolutional compactors.
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2005Analysis of pseudo-interleaving AWG.
Hideo Okawara
2005Analyzing second-order effects between optimizations for system-level test-based model generation.
Tiziana Margaria, Harald Raffelt, Bernhard Steffen
2005Automated mapping of pre-computed module-level test sequences to processor instructions.
S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham
2005Bead probes in practice.
Kenneth P. Parker
2005Board and system test with SoC DFT.
Gordon D. Robinson
2005Built-in constraint resolution.
Grady Giles, Joel Irby, Daniela Toneva, Kun-Han Tsai
2005Burn-in reduction using principal component analysis.
Amit Nahar, W. Robert Daasch, Suresh Subramaniam
2005Business constraints drive test decisions - not vice versa.
Sanjiv Taneja
2005Business constraints drive test decisions planning, partnerships and success.
Michael Campbell
2005Business constraints drive test decisions.
Paul Domino
2005Business constraints drive test decisions.
Fidel Muradali
2005CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system.
Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe
2005Calibrating clock stretch during AC scan testing.
Jeff Rearick, Richard Rodgers
2005Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASIC.
Joel Lurkins, DeAnna Hill, Brady Benware
2005Chasing subtle embedded RAM defects for nanometer technologies.
Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee
2005Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains.
Hung-Mao Lin, James Chien-Mo Li
2005Comparative study of CA with phase shifters and GLFSRs.
S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan
2005Compressed pattern diagnosis for scan chain failures.
Yu Huang, Wu-Tung Cheng, Janusz Rajski
2005Compression mode diagnosis enables high volume monitoring diagnosis flow.
Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai
2005Computational intelligence based testing for semiconductor measurement systems.
Eric Liau, Doris Schmitt-Landsiedel
2005Correct by construction is guaranteed to fail.
Stephen K. Sunter
2005Cost-effective designs of field service for electronic systems.
Yu-Ting Lin, David Williams, Tony Ambler
2005Darwin, thy name is system.
Craig Force
2005Data-driven models for statistical testing: measurements, estimates and residuals.
W. Robert Daasch, Robert Madge
2005Defect-based RF testing using a new catastrophic fault model.
Erkan Acar, Sule Ozev
2005Defect-oriented testing and diagnosis of digital microfluidics-based biochips.
Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
2005Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain.
Tom Waayers, Richard Morren, Roberto Grandi
2005Definitions of jitter measurement terms and relationships.
Iliya Zamek, Steve Zamek
2005Design and analysis of multiple weight linear compactors of responses containing unknown values.
Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara
2005Development of a software framework for open architecture ATE.
William Fritzsche
2005Diagnosis and analysis of an analog circuit failure using time resolved emission microscopy.
Ahmed Syed, Richard F. Herlein, Ben Cain, Frank Sauk
2005Diagnosis framework for locating failed segments of path delay faults.
Ying-Yen Chen, Min-Pin Kuo, Jing-Jia Liou
2005Diagnosis with convolutional compactors in presence of unknown states.
Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2005Drive only at speed functional testing; one of the techniques Intel is using to control test costs.
Mike Tripp, Silvio Picano, Baruch Schnarch
2005Effect of lead free solders on in-circuit test process.
Rosa D. Reinosa
2005Efficient SAT-based combinational ATPG using multi-level don't-cares.
Nikhil Saluja, Sunil P. Khatri
2005Efficient compression of deterministic patterns into multiple PRPG seeds.
Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
2005Enabling yield analysis with X-compact.
Zoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman
2005Encounter test OPMISR
Brion L. Keller
2005Enhanced launch-off-capture transition fault testing.
Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar
2005Evaluating ATE-equipment for volume diagnosis.
Ralf Arnold, Andreas Leininger
2005External memory BIST for system-in-package.
Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta
2005Forming N-detection test sets from one-detection test sets without test generation.
Irith Pomeranz, Sudhakar M. Reddy
2005Full-speed field-programmable memory BIST architecture.
Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005Functional vs. multi-VDD testing of RF circuits.
Estella Silva, José Pineda de Gyvez, Guido Gronthoud
2005Gate exhaustive testing.
Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
2005Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither?
Mani Soma
2005Have we overcome the challenges associated with SoC and multi-core testing?
Rajesh Raina
2005Have we overcome the challenges associated with SoC and multi-core testing?
Rajesh Raina
2005Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects.
Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir
2005Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study.
Jeff Remmers, Darin Lee, Richard Fisette
2005High speed differential pin electronics over 6.4 Gbps.
Atsushi Oshima, Toshihiro Nomura
2005High-performance ADC linearity test using low-precision signals in non-stationary environments.
Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Randall L. Geiger, Degang Chen
2005How are we going to test SOC's on a board?
Michael J. Smith
2005How are we going to test SoC's on a PCB?
Peter Collins
2005How are we going to test SoCs on a board?: the users viewpoint.
Gunnar Carlsson
2005How are we going to test socs on a board? the users viewpoint.
Gunnar Carlsson
2005I
Bin Xue, D. M. H. Walker
2005IEEE 1500 utilization in SOC design and test.
Yervant Zorian, Avetik Yessayan
2005IJTAG (internal JTAG): a step toward a DFT standard.
Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts
2005Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis.
Chris Schuermyer, Kevin Cota, Robert Madge, Brady Benware
2005Impact of back side circuit edit on active device performance in bulk silicon ICs.
Uwe Kerst, Rudolf Schlangen, A. Kabakow, Erwan Le Roy, Ted R. Lundquist, Siegfried Pauthner
2005Invisible delay quality - SDQM model lights up what could not be seen.
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
2005Is the concern for soft-error overblown?
Rajesh Galivanche
2005Is the concern for soft-error overblown?
Rajesh Raina
2005Is the concern for soft-error overblown?
Rajesh Raina
2005JTAG-based vector and chain management for system test.
Bradford G. Van Treuren, Bryan E. Peterson, José M. Miranda
2005Jitter spectrum analysis using continuous time interval analyzer (CTIA).
Sassan Tabatabaei, Freddy Ben-Zeev, Touraj Farahmand
2005Jitter transformations in measurement instruments and discrepancies between measurement results.
Iliya Zamek, Steve Zamek
2005Layering of the STIL extensions.
Gregory A. Maston, Tony Taylor
2005Logic proximity bridges.
Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty
2005Logic soft errors: a major barrier to robust platform design.
Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim
2005Low cost multisite testing of quadruple band GSM transceivers.
Larry Zhang, Dale Heaton, Hank Largey
2005Low-capture-power test generation for scan-based at-speed testing.
Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniers.
Brian Arkin
2005March AB, March AB1: new March tests for unlinked dynamic memory faults.
Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2005Methods for improving test compression.
Nur A. Touba
2005Methods for improving transition delay fault coverage using broadside tests.
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005Microprocessor silicon debug based on failure propagation tracing.
Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu
2005Multiple tests for each gate delay fault: higher coverage and lower test application cost.
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2005Needs fabless yield ramp foundry partnership to be most successful.
Bruce Cory
2005Node sensitivity analysis for soft errors in CMOS logic.
Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff, Norbert Seifert
2005Noncontact wafer probe using wireless probe cards.
Chris Sellathamby, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Steven Slupsky, Igor M. Filanovsky, Kris Iniewski
2005Off-shore outsource DFT vs. build off-shore branch offices.
Yu Huang
2005On concurrent test of wrapped cores and unwrapped logic blocks in SOCs.
Qiang Xu, Nicola Nicolici
2005Optimized reasoning-based diagnosis for non-random, board-level, production defects.
Carlos O'Farrill, Merouane Moakil-Chbany, Bill Eklow
2005Outsourcing DFT: it can be done but it isn't easy.
LeRoy Winemberg
2005Outsourcing DFT: the right mix.
Carl Holzwarth
2005Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?".
Nathan Chelstrom
2005Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail?
Hosam Haggag, Abhijit Chatterjee
2005Panel: business constraints drive test decisions.
Jeff Schneider
2005Parallel, multi-DUT testing in an open architecture test system.
Toshiaki Adachi, Ankan K. Pramanick, Mark Elston
2005Partnering with customer to achieve high yield.
James Wang
2005Position statement: "have we overcome the challenges associated with SoC and multi-core testing?".
Tim Wood
2005Power-scan chain: design for analog testability.
Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, José Pineda de Gyvez
2005Power-supply noise in SoCs: ATPG, estimation and control.
Mehrdad Nourani, Arun Radhakrishnan
2005Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005
2005Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDF.
Soumendu Bhattacharya, Rajarajan Senguttuvan, Abhijit Chatterjee
2005Production-oriented interface testing for PCI-Express by enhanced loop-back technique.
Mitchell Lin, Kwang-Ting Cheng, Jimmy Hsu, M. C. Sun, Jason Chen, Shelton Lu
2005Programmable memory BIST.
Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa
2005Progressive random access scan: a simultaneous solution to test power, test data volume and test time.
Dong Hyun Baik, Kewal K. Saluja
2005Reconfigurable systems self-healing using mobile hardware agents.
Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilárd Enyedi
2005Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail?
Mustapha Slamani
2005Reducing test cost through the use of digital testers for analog tests.
John Sweeney, Alan Tsefrekas
2005Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy
2005Remote boundary-scan system test control for the ATCA standard.
David Bäckström, Gunnar Carlsson, Erik Larsson
2005STIL persistence [data reduction].
Greg Maston, Julie Villar
2005Safely backdriving low voltage devices at in-circuit test.
Chris Jacobsen, Tony Saye, Tom Trader
2005Simulation of transients caused by single-event upsets in combinational logic.
Kartik Mohanram
2005Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen
2005Soft errors: is the concern for soft-errors overblown?
Narayanan Vijaykrishnan
2005Structural tests for jitter tolerance in SerDes receivers.
Stephen K. Sunter, Aubin Roy
2005Synthesis of nonintrusive concurrent error detection using an even error detecting function.
Avijit Dutta, Nur A. Touba
2005Technique to improve the performance of time-interleaved A-D converters.
Koji Asami
2005Test and debug features of the RTO7 chip.
Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld
2005Test compression - real issues and matching solutions.
Janusz Rajski
2005Test compression and logic BIST at your fingertips.
Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu
2005Test connections - tying application to process.
John M. Carulli Jr., Thomas J. Anderson
2005Test data compression for IP embedded cores using selective encoding of scan slices.
Zhanglei Wang, Krishnendu Chakrabarty
2005Test generation for ultra-high-speed asynchronous pipelines.
Feng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh
2005Test implications of lead-free implementation in a high-volume manufacturing environment.
Shu Peng, Sam Wong
2005Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture.
Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan
2005Test the test experts: do we know what we are doing?
Rohit Kapur
2005Test time reduction of successive approximation register A/D converter by selective code measurement.
Shalabh Goyal, Abhijit Chatterjee, Mike Atia, Howard Iglehart, Chung Yu Chen, Bassem Shenouda, Nash Khouzam, Hosam Haggag
2005Testability features of the first-generation CELL processor.
Mack W. Riley, Louis B. Bushard, Nathan Paul Chelstrom, Naoki Kiryu, Steven Ross Ferguson
2005Testing and debugging delay faults in dynamic circuits.
Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham
2005Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.
Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski
2005Testing priority address encoder faults of content addressable memories.
Jin-Fu Li
2005Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field.
Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar
2005The ITC test compression shootout.
Scott Davidson
2005The PXI carrier: a novel approach to ATE instrument development.
Eric Kushnick
2005The case for outsourcing DFT.
Jeffrey L. Roehr
2005The concern for soft errors is not overblown.
Pia N. Sanda
2005The effects of defects on high-speed boards.
Kenneth P. Parker
2005The final D-frontier: should DFT be outsourced?
Luis Basto
2005The value of statistical testing for quality, yield and test cost improvement.
Robert Madge, Brady Benware, Mark Ward, W. Robert Daasch
2005Third-Order Phase Lock Loop Measurement and Characterization.
J. Ma, M. Li, M. Marlett
2005Today's SOC test challenges.
Yervant Zorian
2005Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and "cost, cost, cost"...: making peace between a black art and the bottom line.
Jody Van Horn
2005Transient fault characterization in dynamic noisy environments.
Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
2005UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.
Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang
2005Understanding NTF components from the field.
Scott Davidson
2005Use of MISRs for compression and diagnostics.
Brion L. Keller, Thomas Bartenstein
2005Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics.
Zhanglei Wang, Krishnendu Chakrabarty
2005Variance reduction and outliers: statistical analysis of semiconductor test data.
W. Robert Daasch, Robert Madge
2005Verifying flying prober performance - fitness is survival.
Bob Russell
2005Word line pulsing technique for stability fault detection in SRAM cells.
Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev
2005X-filter: filtering unknowns from compacted test responses.
Manish Sharma, Wu-Tung Cheng
2005XMAX: a practical and efficient compression architecture.
Kee Sup Kim
2005XWRC: externally-loaded weighted random pattern testing for input test data compression.
Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar