ITC A

208 papers

YearTitle / Authors
2004"Real Life" System Testing of Networking Equipment.
Sunil Kalidindi, Nghia Huynh, Bill Eklow, Josh Goldstein
2004100 DPPM in Nanometer Technology - Is it achievable?
Greg Aldrich
20042003 Paper Awards.
20042005 Call for Papers.
200434.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System.
Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu
2004A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems.
C. J. Clark, Mike Ricchetti
2004A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent Sampling.
Zhongjun Yu, Degang Chen, Randall L. Geiger
2004A Critical Path Selection Method for Delay Testing.
Saravanan Padmanaban, Spyros Tragoudas
2004A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
2004A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis.
Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal
2004A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4.
Juha Häkkinen, Pekka Syri, Juha-Veikko Voutilainen, Markku Moilanen
2004A Hierarchical DFT Architecture for Chip, Board and System Test/Debug.
Charles Njinda
2004A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme.
Peter M. Levine, Gordon W. Roberts
2004A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing.
Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sébastien Laberge, Gordon W. Roberts
2004A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
C. P. Ravikumar, Graham Hetherington
2004A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals.
Jim Sproch
2004A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC Devices.
Bernd Laquai
2004A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories.
Robert C. Aitken
2004A New Probing Technique for High-Speed/High-Density Printed Circuit Boards.
Kenneth P. Parker
2004A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current.
Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia
2004A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems.
Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai
2004AC IO Loopback Design for High Speed µProcessor IO Test.
Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono
2004ALAPTF: A new Transition Faultmodel and the ATPG Algorithm.
Puneet Gupta, Michael S. Hsiao
2004AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
2004ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test.
Manu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw
2004ATE Value Add through Open Data Collection.
Robert Madge
2004Achieving Quality Levels of 100dpm: It's possible - but roll up your sleeves and be prepared to do some work..
Phil Nigh
2004Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs.
Brady Benware
2004Active Tester Interface Unit Design For Data Collection.
A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran
2004Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.
Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
2004An Automated, Complete, Structural Test Solution for SERDES.
Stephen K. Sunter, Aubin Roy, Jean-Francois Cote
2004An Economic Analysis and ROI Model for Nanometer Test.
Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane
2004An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor.
David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher
2004An SOC Test Integration Platform and Its Industrial Realization.
Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
2004Analysis of delay caused by bridging faults in RLC interconnects.
Quming Zhou, Kartik Mohanram
2004Application-Dependent Diagnosis of FPGAs.
Mehdi Baradaran Tahoori
2004Architectures of Increased Availability Wireless Sensor Network Nodes.
Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka
2004At-Speed Interconnect Test and Diagnosis of External Memories on a System.
Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung
2004Automatic Delay Calibration Method for Multi-channel CMOS Formatter.
Ahmed Rashid Syed
2004Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer.
Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi
2004Autonomous Yet Deterministic Test of SOC Cores.
Ozgur Sinanoglu, Alex Orailoglu
2004BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics.
Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng
2004Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
2004Board Test Coverage Needs to be Standardized.
Kenneth P. Parker
2004Built-In Self-Test for System-on-Chip: A Case Study.
Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris
2004CAEN-BIST: Testing the NanoFabric.
Jason G. Brown, R. D. (Shawn) Blanton
2004CMOS IC diagnostics using the luminescence of OFF-state leakage currents.
Stas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho
2004Channel Masking Synthesis for Efficient On-Chip Test Compression.
Vivek Chickermane, Brian Foutz, Brion L. Keller
2004Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays.
Fei Su, Krishnendu Chakrabarty
2004Controlled Sine Wave Fitting for ADC Test.
Heinz Mattes, Claus Dworski, Sebastian Sattler
2004Cost of Test - Taking Control.
Nilanjan Mukherjee
2004DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.
K. Nikila, Rubin A. Parekhji
2004Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.
Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand
2004Data Mining Integrated Circuit Fails with Fail Commonalities.
Leendert M. Huisman, Maroun Kassab, Leah Pastel
2004Decision Selection and Learning for an All-Solutions ATPG Engine.
Kameshwar Chandrasekar, Michael S. Hsiao
2004Defect Coverage Analysis of Partitioned Testing.
Sreejit Chakravarty, Eric W. Savage, Eric N. Tran
2004Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.
Chintan Patel, Abhishek Singh, Jim Plusquellic
2004Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis.
Erkan Acar, Sule Ozev
2004Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.
Ad J. van de Goor, Said Hamdioui, Rob Wadsworth
2004Diagnosis Meets Physical Failure Analysis: How Long can we Succeed?
Anne E. Gattiker
2004Diagnosis meets Physical Failure Analysis: What is needed to succeed?
Srikanth Venkataraman
2004Digital Synchronization for Reconfigurable ATE.
Burnell G. West, Michael F. Jones
2004Divide and Conquer based Fast Shmoo algorithms.
Peter Patten
2004Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester.
W. Robert Daasch, Manu Rehani
2004Efficient Pattern Mapping for Deterministic Logic BIST.
Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
2004Electronic circuit comprising a secret sub-module.
Hérvé Fleury
2004Elimination of Traditional Functional Testing of Interface Timings at Intel.
Mike Tripp, T. M. Mak, Anne Meixner
2004Embedded Test for a new Memory-Card Architecture.
David Resnick
2004Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.
Haihua Yan, Adit D. Singh
2004Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems.
Fulvio Corno, Matteo Sonza Reorda, Simonluca Tosato, F. Esposito
2004Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor.
M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee
2004Experimental Results for High-Speed Jitter Measurement Technique.
Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz
2004Extending STIL 1450 Standard for Test Program Flow.
David Dowding, Ernie Wahl, Don Organ
2004Extending the Digital Core-based Test Methodology to Support Mixed-Signal.
Geert Seuren, Tom Waayers
2004Fault Diagnosis in Designs with Convolutional Compactors.
Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
2004Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2004Feed Forward Test Methodology Utilizing Device Identification.
A. Cabbibo, J. Conder, M. Jacobs
2004Formal Description of Test Specification and ATE Architecture for Mixed-Signal Test.
Baolin Deng, Wolfram Glauert
2004Formal Verification of a System-on-Chip Using Computation Slicing.
Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra
2004Functional Test Coverage Effectiveness on the Decline.
Jay J. Nejedlo
2004Future Trends in Test: The Adoption and Use of Low Cost Structural Testers.
Alfred L. Crouch
2004Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem?
Mohamed Hafed
2004Global Failure Localization: We Have To, But on What and How?
Edward I. Cole Jr.
2004Hierarchical DFT Methodology - A Case Study.
Jeff Remmers, Moe Villalba, Richard Fisette
2004How long can we succeed using the OBIRCH and its derivatives?
Kiyoshi Nikawa
2004How to Bridge the Gap Between Simulationand Test.
Martin Zambaldi, Wolfgang Ecker
2004I/O Self-Leakage Test.
Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor
2004IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2004IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.
Saghir A. Shaikh
2004IPV6 Conformance Testing: Theory and Practice.
Yujun Zhang, Zhongcheng Li
2004ITC 2004 Panel: Cost of Test - Taking Control.
Mike Tripp
2004ITC Technical Paper Evaluation and Selection Process.
2004Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.
Manan Syal, Michael S. Hsiao, Sreejit Chakravarty
2004Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
Bipul Chandra Paul, Cassondra Neau, Kaushik Roy
2004Impact of Negative Bias Temperature Instability on Product Parametric Drift.
Vijay Reddy, John M. Carulli, Anand T. Krishnan, William Bosch, Brendan Burgess
2004Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE.
Gert Hansel, Korbinian Stieglbauer
2004Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion.
Kedarnath J. Balakrishnan, Nur A. Touba
2004In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost.
Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler
2004Integrating Boundary Scan into Multi-GHz I/O Circuitry.
Jeff Rearick, Sylvia Patterson, Krista Dorner
2004Integrating Core Selection in the SOC Test Solution Design-Flow.
Erik Larsson
2004Interconnect Delay Testing of Designs on Programmable Logic Devices.
Mehdi Baradaran Tahoori, Subhasish Mitra
2004Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors.
Kendrick Baker, Mehrdad Nourani
2004International Test Conference - Copyright.
2004International Test Conference - Cover.
2004International Test Conference - Title Page.
2004Investment vs. Yield Relationship for Memories and IP in SOC.
Joseph A. Reynick
2004Investment vs. Yield Relationship for Memories in SOC.
Yervant Zorian
2004Is "Design to Production" The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?
Mike Li
2004Jitter Generation and Measurement for Test of Multigbps Serial IO.
Sassan Tabatabaei, Michael Lee, Freddy Ben-Zeev
2004Jitter Models and Measurement Methods for High-Speed Serial Interconnects.
Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei
2004K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
2004Localizing Open Interconnect Defects using Targeted Routing in FPGA's.
Dave Mark, Jenny Fan
2004Logic BIST with Scan Chain Segmentation.
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2004Loopback or not?
Takahiro J. Yamaguchi
2004Low Cost Concurrent Error Detection for the Advanced Encryption Standard.
Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel
2004Low Overhead Delay Testing of ASICS.
Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley
2004MRAM Defect Analysis and Fault Modeli.
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
2004Memory Yield Improvement - SoC Design Perspective.
Jitendra Khare
2004Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.
Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington
2004Minimum Testing Requirements to Screen Temperature Dependent Defects.
Chris Schuermyer, Jens Ruffler, W. Robert Daasch
2004Modular Extension of ATE to 5 Gbps.
David C. Keezer, Dany Minier, F. Binette
2004Ned Kornfield Memorial.
2004New Test Paradigms for Yield and Manufacturability.
Robert Madge
2004Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions.
Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow
2004On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
2004On Hazard-free Patterns for Fine-delay Fault Testing.
Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
2004On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits.
Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
2004On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing.
Abhishek Singh, Chintan Patel, Jim Plusquellic
2004On-Chip Mixed-Signal Test Structures Re-used for Board Test.
Rodger Schuttert, D. C. L. (Erik) van Geest, A. Kumar
2004On-line Testing Field Programmable Analog Array Circuits.
Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas
2004Open Architecture ATE: Dream or Reality?
Gordon D. Robinson
2004Open Architecture ATE: Prospects and Problems.
Burnell G. West
2004Open Architecture Test System: System Architecture and Design.
Rochit Rajsuman, Masuda Noriyuki
2004Options for High-Volume Test of Multi-GB/s Ports.
John C. Johnson
2004Panel 9 - Diagnostics vs. Failure Analysis.
Thomas Bartenstein
2004Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?
Yukio Okuda
2004Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation.
Hak-Soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
2004Plan Ahead for Yield.
Jun Qian
2004Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM.
Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii
2004Power Supply Ramping for Quasi-static Testing of PLLs.
José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller
2004Practical Instrumentation Integration Considerations.
Thomas J. Anderson
2004Precise Pulse Width Measurement in Write Pre-compensation Test.
Hideo Okawara
2004Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies.
Amit Verma, Charles Robinson, Steve Butkovich
2004Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.
Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi
2004Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.
Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee
2004RF Testing on a Mixed Signal Tester.
Dana Brown, John Ferrario, Randy Wolf, Jing Li, Jayendra Bhagat
2004Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions.
Phil Nigh, Anne E. Gattiker
2004Realizing High Test Quality Goals with Smart Test Resource Usage.
Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
2004Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization".
Phil Nigh
2004Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test Time.
Christopher S. Taillefer, Gordon W. Roberts
2004Reducing Power Consumption in Memory ECC Checkers.
Shalini Ghosh, Nur A. Touba, Sugato Basu
2004Removing JTAG Bottlenecks in System Interconnect Test.
Hong Shin Jun, Sung Soo Chung, Sang H. Baeg
2004Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.
Cecilia Metra, T. M. Mak, Martin Omaña
2004Routability and Fault Tolerance of FPGA Interconnect Architectures.
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi
2004SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits.
Feng Shi, Yiorgos Makris
2004Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.
Bo Yang, Kaijie Wu, Ramesh Karri
2004Security vs. Test Quality: Are they mutually exclusive?
Rohit Kapur
2004Security vs. Test Quality: Can We Really Only Have One at a Time?
Erik Jan Marinissen
2004Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.
Stephen Pateras
2004Simulation Based System Level Fault Insertion Using Co-verification Tools.
Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau
2004Simulation Requirements for Vectors in ATE Formats.
R. Raghuraman
2004Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.
Omar I. Khan, Michael L. Bushnell
2004Speed Clustering of Integrated Circuits.
Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra
2004State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation.
Qingwei Wu, Michael S. Hsiao
2004Steering Committee and Subcommittees.
2004Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya.
Kenneth M. Butler
2004System Monitor for Diagnostic, Calibration and System Configuration.
Maurizio Gavardoni, Michael Jones, Russell Poffenberger, Miguel Conde
2004Systematic Defects in Deep Sub-Micron Technologies.
Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
2004TTTC: Test Technology Technical Council.
2004Technical Paper Reviewers.
2004Technical Program Committee.
2004Test Cost Reduction Through A Reconfigurable Scan Architecture.
Baris Arslan, Alex Orailoglu
2004Test In the Era of "What You see Is NOT What You Get".
Bernd Koenemann
2004Test Programming Environment in a Modular, Open Architecture Test System.
Ankan K. Pramanick, Ramachandran Krishnaswamy, Mark Elston, Toshiaki Adachi, Harsanjeet Singh, Bruce R. Parnas
2004Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan
2004Test Strategies For a 40Gbps Framer SoC.
Hans T. Heineken, Jitendra Khare
2004Test Strategies for Nanometer Technologies.
Sanjay Sengupta
2004Test Strategy Cost Model Innovations.
Carlos Michel, Rosa D. Reinosa
2004Tester Architecture For The Source Synchronous Bus.
A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson
2004Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACs.
Hanjun Jiang, Beatriz Olleta, Degang Chen, Randall L. Geiger
2004Testing Micropipelined Asynchronous Circuits.
Matthew L. King, Kewal K. Saluja
2004Testing a secure device: High coverage with very low observability.
Laurent Sourgen
2004Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.
Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung
2004Testing in a high volume DSM Environment.
Thomas M. Storey
2004Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.
Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
2004The Critical Need For Open ATE Architecture.
Sergio M. Perez
2004The Leading Edge of Production Wafer Probe Test Technology.
William R. Mann, Frederick L. Taber, Philip W. Seitzer, Jerry J. Broz
2004Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores.
Qiang Xu, Nicola Nicolici
2004Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE.
Masashi Shimanouchi
2004Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2004To Test or To Inspect, What is the Coverage?
Rob Jukna
2004Towards Microagent based DBIST/DBISR.
Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto
2004Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications.
Mike Li, Andy Martwick, Gerry Talbot, Jan B. Wilstrup
2004Trends in Testing Integrated Circuits.
Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
2004Trends in manufacturing test methods and their implications.
Sandip Kundu, T. M. Mak, Rajesh Galivanche
2004Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu
2004Use of Embedded Sensors for Built-In-Test of RF Circuits.
Soumendu Bhattacharya, Abhijit Chatterjee
2004Verification on Port Connections.
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
2004VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
2004Welcoming Message.
2004What Do You Mean My Board Test Stinks?
Bill Eklow
2004What do you mean my Board Test stinks?
Michael J. Smith
2004Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?
Mike Li
2004Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
2004X-Masking During Logic BIST and Its Impact on Defect Coverage.
Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
2004X-Tolerant Signature Analysis.
Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher
2004Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
2003Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA