ITC A

189 papers

YearTitle / Authors
2002A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
2002A Multi-Language Goal-Tree Based Functional Test Planning System.
Rajneesh Mahajan, Ramesh Govindarajulu, James R. Armstrong, F. Gail Gray
2002A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.
A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre
2002A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter.
Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie
2002A New Test Generation Approach for Embedded Analogue Cores in SoC.
M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff
2002A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.
Tapan J. Chakraborty, Chen-Huan Chiang
2002A Persistent Diagnostic Technique for Unstable Defects.
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
2002A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC
Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
2002A Set of Benchmarks fo Modular Testing of SOCs.
Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
2002A Structured Graphical Tool for Analyzing Boundary Scan Violations.
Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora
2002A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.
Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
2002A Wavelet-Based Timing Parameter Extraction Method.
Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina
2002A/MS BISTs: The FACTS, Just the Facts.
Arnold Frisch
2002Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development.
Tom Austin, Charisma Canlas, Brady Morgan, Jorge L. Rodriguez
2002Adapting an SoC to ATE Concurrent Test Capabilities.
Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer
2002An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.
Zhigang Jiang, Sandeep K. Gupta
2002An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.
Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née
2002An Effective Diagnosis Method to Support Yield Improvement.
Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg
2002An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning.
David Berthelot, Samit Chaudhuri, Hamid Savoj
2002An Embedded Core for Sub-Picosecond Timing Measurements.
Sassan Tabatabaei, André Ivanov
2002An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.
Dave Stang, Ramaswami Dandapani
2002An Integrated Approach to Yield Loss Characterization.
Mark Craig, Alvin Jee, Prashant Maniar
2002An Open Architecture for Semiconductor Test: Enablers and Challenges.
Mark Jagiela
2002Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.
Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
2002Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002Application of High-Quality Built-In Test to Industrial Designs.
Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
2002Architecting Millisecond Test Solutions for Wireless Phone RFIC's.
John Ferrario, Randy Wolf, Steve Moss
2002Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.
Jayanta Bhadra, Narayanan Krishnamurthy
2002Automatic Scan Insertion and Test Generation for Asynchronous Circuits.
Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff
2002BIST-Based Diagnosis of FPGA Interconnect.
Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
2002Board Test Is NOT Mature.
Kenneth P. Parker
2002Board Test: Wanted Dead or Alive.
Gordon D. Robinson
2002Built-In Self Test of CMOS-MEMS Accelerometers.
Nilmoni Deb, R. D. (Shawn) Blanton
2002CMOS Circuit Technology for Precise GHz Timing Generator.
Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto
2002Can IC Test Learn from How a Tester is Tested.
Rochit Rajsuman
2002Challenges and Solutions for Multi-Gigahertz Testing.
David C. Keezer
2002Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs.
Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura
2002Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.
Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
2002Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
2002Comparison of IDDQ Testing and Very-Low Voltage Testing.
Bram Kruseman, Stefan van den Oetelaar, Josep Rius
2002Compensation of Transmission Line Loss for Gbit/s Test on ATEs.
Wolfram Humann
2002Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.
Stephen K. Sunter, Benoit Nadeau-Dostie
2002Considerations for STIL Data Application.
Gregory A. Maston
2002Core-Based Scan Architecture for Silicon Debug.
Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
2002DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka
2002DUT Capture Using Simultaneous Logic Acquisition.
A. T. Sivaram, William Fritzsche, Toshitaka Koshi, Nam Lai
2002Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.
Mohsen Nahvi, André Ivanov, Resve A. Saleh
2002Design Rewiring Using ATPG.
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
2002Diagonal Test and Diagnostic Schemes for Flash Memorie.
Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2002EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.
Bart Vermeulen, Tom Waayers, Sjaak Bakker
2002Effective and Efficient Test Architecture Design for SOCs.
Sandeep Kumar Goel, Erik Jan Marinissen
2002Efficient Design of System Test: A Layered Architecture.
Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
2002Efficient Embedded Memory Testing with APG.
A. T. Sivaram, Daniel Fan, A. Yiin
2002Embedded Deterministic Test for Low-Cost Manufacturing Test.
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
2002Embedded Memory Test and Repair: Infrastructure IP for SOC Yield.
Yervant Zorian
2002Experimental Evaluation of Scan Tests for Bridges.
Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah
2002FPGA Test and Coverage.
Shahin Toutounchi, Andrew Lai
2002FRITS - A Microprocessor Functional BIST Method.
Praveen Parvathala, Kaila Maneparambil, William Lindsay
2002Facilitating Rapid First Silicon Debug.
Hari Balachandran, Kenneth M. Butler, Neil Simpson
2002Fault Grading FPGA Interconnect Test Configurations.
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
2002Fault Tuples in Diagnosis of Deep-Submicron Circuits.
Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
2002Finding a Small Set of Longest Testable Paths that Cover Every Gate.
Manish Sharma, Janak H. Patel
2002Frequency/Phase Movement Analy i by Orthogonal Demodulation.
Hideo Okawara
2002GHz Testing and Its Fuzzy Targets.
Chuck Hawkins, Jaume Segura
2002Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.
Seongmoon Wang
2002Good Scan = Good Quality Level? Well, It Depends ?
Anjali Kinra Vij
2002Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.
Sandeep Kumar Goel, Bart Vermeulen
2002High Accuracy Stimulus Generation for A/D Converter BIST.
Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello
2002High Current DPS Architecture for Sort Test Challenge.
Jean-Pascal Mallet
2002Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.
Bozena Kaminska
2002Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.
Dale E. Hoffman
2002Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.
Bill Bottoms
2002Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.
Gregory S. Spirakis
2002IC Mixed-Signal BIST: Separating Facts from Fiction.
Stephen K. Sunter
2002IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.
Bill Eklow, Carl Barnhart, Kenneth P. Parker
2002Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs.
Carsten Wegener, Michael Peter Kennedy
2002Improved Digital I/O Ports Enhance Testability of Interconnections.
Adam Kristof
2002Improved IDDQ Testing with Empirical Linear Prediction.
David I. Bergman, Hans Engler
2002Incremental Diagnosis of Multiple Open-Interconnects.
Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi
2002Inevitable Use of TAP Domains in SOCs.
Lee Whetsel
2002Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2002Integrating DFT in the Physical Synthesis Flow.
Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
2002Integration of SRAM Redundancy into Production Test.
Jayasanker Jayabalan, Juraj Povazanec
2002Is Board Test Worth Talking About?
Bill Eklow
2002Is ITC Bored with Board Test?
Kenneth M. Butler
2002Is It Rocket Science?
Anthony P. Ambler
2002Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It.
Grady Giles
2002Is an Open Architecture Tester Really Achievable?
Paul D. Roddy
2002Isolating and Removing Sources of Variation in Test Data.
David Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge
2002Itelligent Agents and BIST/BISR - Working Together in Distributed Systems.
Liviu Miclea, Szilárd Enyedi, Alfredo Benso
2002Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter.
Yi Cai, S. A. Werner, G. J. Zhang, Max J. Olsen, Robert D. Brink
2002Low-Contact-Force Probing on Copper Electrodes.
Kenichi Kataoka, Toshihiro Itoh, Katsuya Okumura, Tadatomo Suga
2002Managing in the ATE Business - Postcards from the Past, Lessons for the Future.
Alex d'Arbeloff
2002Mission Impossible? Open Architecture ATE.
Dennis R. Conti
2002Mission Possible? Open Architecture ATE.
Paul F. Scrivens
2002Mixed Signal BIST: Fact or Fiction.
Lee Y. Song
2002Mixed-Signal BIST: Fact or Fiction.
Karim Arabi
2002Mixed-Signal BIST: Fact or Fiction.
Gordon W. Roberts
2002Multi-GHz interface devices should be tested using external test resources.
Takahiro J. Yamaguchi
2002Multi-Gigahertz Digital Test Challenges and Techniques.
Manoj Sachdev
2002Multi-Gigahertz Digital Test Challenges and Techniques.
Ulrich Schoettmer
2002Multi-Purpose Digital Test Core Utilizing Programmable Logic.
John S. Davis, David C. Keezer
2002Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis.
David B. Lavo, Ismed Hartanto, Tracy Larrabee
2002Multiscan-Based Test Compression and Hardware Decompression Using LZ77.
Francis G. Wolff, Christos A. Papachristou
2002Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.
W. Robert Daasch, Kevin Cota, James McNames, Robert Madge
2002New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.
Masashi Shimanouchi
2002On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.
Ramesh C. Tekumalla, Scott Davidson
2002On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
Li-C. Wang, Magdy S. Abadir, Juhong Zhu
2002On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2002On the Accuracy of Jitter Separation from Bit Error Rate Function.
Mike Peng Li, Jan B. Wilstrup
2002On the Use of k-tuples for SoC Test Schedule Representation.
Sandeep Koranne, Vikram Iyengar
2002On-Chip Repair and an ATE Independent Fusing Methodology.
Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater
2002On-Die DFT Based Solutions are Sufficient for Testing Multi-GHz Interfaces in Manufacturing (and Are Also Key to Enabling Lower Cost ATE Platforms).
Mike Tripp
2002On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.
Yi Zhao, Li Chen, Sujit Dey
2002Open ATE Architecture: Key Challenges.
Burnell G. West
2002Optimal BIST Using an Embedded Microprocessor.
Sungbae Hwang, Jacob A. Abraham
2002Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002Outsourcing Test without Standards?
Peter Muhmenthaler
2002Packet-Based Input Test Data Compression Techniques.
Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
2002Panel: "Board Test and ITC: What Does the Future Hold?".
Monica Lobetti Bodoni
2002Parametric Failures in CMOS ICs - A Defect-Based Analysis.
Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
2002Physical Principles of Interface Design.
Todd Sargent
2002Power Driven Chaining of Flip-Flops in Scan Architectures.
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2002Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002
2002Pseudo Random Patterns Using Markov Sources for Scan BIST.
Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002R4X/D4X - Formatters for Flexible Test System Architecture.
Ahmed Rashid Syed
2002RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
2002Re-Using DFT Logic for Functional and Silicon Debugging Test.
Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung
2002Realistic Spring Probe Testing Methods and Results.
David Gessel, Alexander H. Slcoum, Alexander D. Sprunt, Scott Ziegenhagen
2002Realizing the Benefits of Structural Test for Intel Microprocessors.
Mike Mayberry, John Johnson, Navid Shahriari, Mike Tripp
2002Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression.
C. V. Krishna, Nur A. Touba
2002Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.
Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
2002Robustness IPs for Reliability and Security of SoCs.
Eric Dupont, Michael Nicolaidis
2002Scan Power Reduction Through Test Data Transition Frequency Analysis.
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.
Vishal Jain, John A. Waicukauski
2002Scan and BIST Can Almost Achieve Test Quality Levels.
Carol Pyron
2002Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products.
Phil Nigh
2002Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .
Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech
2002Screening MinVDD Outliers Using Feed-Forward Voltage Testing.
Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner
2002Selective Optimization of Test for Embedded Flash Memory.
Roger Barth
2002Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor.
Mohammad H. Tehranipour, Mehrdad Nourani
2002Silicon Symptoms to Solutions: Applying Design for Debug Techniques.
Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger
2002Static Analysis of SEU Effects on Software Applications.
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2002Support for Debugging in the Alpha 21364 Microprocessor.
Timothe Litt
2002System Manufacturing Test Cost Model.
David Williams, Anthony P. Ambler
2002TAPS All Over My Chips! So Now What Do I Do?
Bart Vermeulen
2002TAPS All Over My Chips.
Teresa L. McLaurin
2002TAPs All Over My Chips.
Steven F. Oakland
2002Techniques to Reduce Data Volume and Application Time for Transition Test.
Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
2002Test Coverage Models for System Test?
David Williams
2002Test Coverage: What Does It Mean When a Board Test Passes?.
Kathy Hird, Kenneth P. Parker, Bill Follis
2002Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.
Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina
2002Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.
M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor
2002Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2002Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements.
Gunter Krampl, Marco Rona, Hermann Tauber
2002Test Time Impact of Redundancy Repair in Embedded Flash Memory.
Paul Okino
2002Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores.
Mohamed M. Hafed, Gordon W. Roberts
2002Test and Repair of Embedded Flash Memories.
Jean Michel Daga
2002Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory).
Riichiro Shirota
2002Test and Repair of Nonvolatile Commodity and Embedded Memories.
Shigeo Tsuchida
2002Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
Bipul Chandra Paul, Kaushik Roy
2002Testing Finite State Machines Based on a Structural Coverage Metric .
Sezer Gören, F. Joel Ferguson
2002Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge?
Mustapha Slamani
2002Testing The Tester.
Rochit Rajsuman
2002Testing The Tester.
Rochit Rajsuman
2002Testing Wireless Local Area Network Transceiver ICs at 5 GHz.
Kevin M. MacKay
2002Testing the Tester: Specification and Validation Approaches.
John C. Johnson
2002Testing the Tester: What Broke? Where? When? Why?
Alfred L. Crouch
2002The Consequences of an Open ATE Architecture.
Sergio M. Perez
2002The Heisenberg Uncertainty of Test.
Peter C. Maxwell
2002The Impact of Outsourcing on Test.
Fidel Muradali
2002The Manic Depression of Microprocessor Debug.
Don Douglas Josephson
2002The Process and Challenges of a High-Speed DUT Board Project.
David E. McFeely
2002The Role of Test in a Highly Outsourced Business Model.
Bill Price
2002The Yield of Test Outsourcing.
Davide Appello
2002Trouble With Scan.
David M. Wu
2002Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .
Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead
2002Use of Pipeline Converters for ATE Applications.
Maurizio Gavardoni
2002Verification of Device Interface Hardware Interconnections Prior to the Start of Testing.
Guy Peterson
2002Verifying Properties Using Sequential ATPG.
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
2002WCDMA Testing with a Baseband/IF Range AWG.
Koji Asami, Yasuo Furukawa, Michael Purtell, Motoo Ueda, Karl Watanabe, Toshifumi Watanabe
2002Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation.
Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill
2002Wafer/Package Test Mix for Optimal Defect Detection.
Peter C. Maxwell
2002What Can IC Test Teach System Test?
Scott Davidson
2002What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region.
Thomas P. Warwick
2002Wireless SOC Testing: Can RF Testing Costs Be Reduced?
Alan Kafton
2002X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.
Subhasish Mitra, Kee Sup Kim
2002XIDEN: Crosstalk Target Identification Framework.
Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2002valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits.
John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns