| 2001 | 99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor. Mary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott |
| 2001 | : Identifying redundant gate replacements in verification by error modeling. Zeljko Zilic, Katarzyna Radecka |
| 2001 | A building block BIST methodology for SOC designs: a case study. Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre |
| 2001 | A built-in timing parametric measurement unit. Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang |
| 2001 | A case study on the implementation of the Illinois Scan Architecture. Frank F. Hsu, Kenneth M. Butler, Janak H. Patel |
| 2001 | A general purpose 1149.4 IC with HF analog test capabilities. Stephen K. Sunter, Ken Filliter, Joe Woo, Pat McHugh |
| 2001 | A high-resolution jitter measurement technique using ADC sampling. Sasikumar Cherubal, Abhijit Chatterjee |
| 2001 | A highly-efficient transparent online memory test. Karl Thaller |
| 2001 | A method to enhance the fault coverage obtained by output response comparison of identical circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | A method to improve SFDR with random interleaved sampling method. Mamoru Tamba, Atsushi Shimizu, Hideharu Munakata, Takanori Komuro |
| 2001 | A new methodology for improved tester utilization. Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir |
| 2001 | A new multiple weight set calculation algorithm. Hong-Sik Kim, Jin-kyue Lee, Sungho Kang |
| 2001 | A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly. Thiagarajan Trichy, Peter Sandborn, Ravi Raghavan, Shubhada Sahasrabudhe |
| 2001 | A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments. Hui S. Nam, Bernard Cuddy, Dieter Luecking |
| 2001 | A practical built-in current sensor for I_DDQ testing. Hoki Kim, D. M. H. Walker, David Colby |
| 2001 | A practical guide to combining ICT & boundary scan testing. Alan Albee |
| 2001 | A stand-alone integrated test core for time and frequency domain measurements. Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts |
| 2001 | A study of bridging defect probabilities on a Pentium (TM) 4 CPU. Venkatram Krishnaswamy, A. B. Ma, Praveen Vishakantaiah |
| 2001 | A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. Antonio H. Chan, Gordon W. Roberts |
| 2001 | A technique for fault diagnosis of defects in scan chains. Ruifeng Guo, Srikanth Venkataraman |
| 2001 | A token scan architecture for low power testing. Tsung-Chu Huang, Kuen-Jong Lee |
| 2001 | A validation fault model for timing-induced functional errors. Qiushuang Zhang, Ian G. Harris |
| 2001 | AC-JTAG: empowering JTAG beyond testing DC nets. Sung Soo Chung, Sanghyeon Baeg |
| 2001 | AMLETO: a multi-language environment for functional test generation. Alessandro Fin, Franco Fummi, Graziano Pravadelli |
| 2001 | Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. Kaijie Wu, Ramesh Karri |
| 2001 | An analysis of power reduction techniques in scan testing. Jayashree Saxena, Kenneth M. Butler, Lee Whetsel |
| 2001 | An approach to consistent jitter modeling for various jitter aspects and measurement methods. Masashi Shimanouchi |
| 2001 | An effort-minimized logic BIST implementation method. Xinli Gu, Sung Soo Chung, Frank Tsang, Jan Arild Tofte, Hamid Rahmanian |
| 2001 | An evaluation of defect-oriented test: WELL-controlled low voltage test. Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto |
| 2001 | At-speed logic BIST using a frozen clock testing strategy. Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici |
| 2001 | Automated translation of legacy code for ATE. Andrew Moran, Jim Teisher, Andrew Gill, Emir Pasalic, John Veneruso |
| 2001 | BIST and fault insertion re-use in telecom systems. Snezana Dikic, Lars-Johan Fritz, Dario Dell'Aquia |
| 2001 | BIST-based delay path testing in FPGA architectures. Ian G. Harris, Premachandran R. Menon, Russell Tessier |
| 2001 | Bitline contacts in high density SRAMs: design for testability and stressability. Harold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers |
| 2001 | Boolean and current detection of MOS transistor with gate oxide short. Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand |
| 2001 | CTL the language for describing core-based test. Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay |
| 2001 | Combinational test generation for various classes of acyclic sequential circuits. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
| 2001 | Configuration free SoC interconnect BIST methodology. Chauchin Su, Wenliang Tseng |
| 2001 | Contactless digital testing of IC pin leakage currents. Stephen K. Sunter, Charles McDonald, Givargis Danialy |
| 2001 | Cost evaluation of coverage directed test generation for the IBM mainframe. Gilly Nativ, Steven Mittermaier, Shmuel Ur, Avi Ziv |
| 2001 | Crosstalk test generation on pseudo industrial circuits: a case study. Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | DPDAT: data path direct access testing. Kee Sup Kim, Rathish Jayabharathi, Craig Carstens, Praveen Vishakantaiah, Derek Feltham, Adrian Carbine |
| 2001 | Debug methodology for the McKinley processor. Don Douglas Josephson, Steve Poehhnan, Vincent Govan |
| 2001 | Delay testing considering crosstalk-induced effects. Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng |
| 2001 | Design of compactors for signature-analyzers in built-in self-test. Peter Wohl, John A. Waicukauski, Thomas W. Williams |
| 2001 | Detecting delay faults using power supply transient signal analysis. Abhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker |
| 2001 | Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski |
| 2001 | Dynamic tests in complex systems [automotive electronics]. Robert Tappe, Dietmar Ehrhardt |
| 2001 | Embedded DRAM built in self test and methodology for test insertion. Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek |
| 2001 | Enhanced reduced pin-count test for full-scan design. Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier |
| 2001 | Estimating burn-in fall-out for redundant memory. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
| 2001 | Exact path delay grading with fundamental BDD operations. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas |
| 2001 | Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement. Mohammad Athar Khalil, Chin-Long Wey |
| 2001 | Fast test generation for circuits with RTL and gate-level views. Srivaths Ravi, Niraj K. Jha |
| 2001 | FedEx - a fast bridging fault extractor. Zoran Stanojevic, D. M. H. Walker |
| 2001 | Frequency detection-based boundary-scan testing of AC coupled nets. Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick |
| 2001 | GRAAL: a tool for highly dependable SRAMs generation. Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari |
| 2001 | Hierarchical boundary-scan: a Scan Chip-Set solution. Stephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood |
| 2001 | IS-FPGA : a new symmetric FPGA architecture with implicit scan. Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 2001 | Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira |
| 2001 | Improved wafer-level spatial analysis for I_DDQ limit setting. Sagar S. Sabade, D. M. H. Walker |
| 2001 | Low hardware overhead scan based 3-weight weighted random BIST. Seongrnoon Wang |
| 2001 | Making cause-effect cost effective: low-resolution fault dictionaries. David B. Lavo, Tracy Larrabee |
| 2001 | March-based RAM diagnosis algorithms for stuck-at and coupling faults. Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2001 | Memory built-in self-repair using redundant words. Volker Schöber, Steffen Paul, Olivier Picot |
| 2001 | Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo. Gilbert Vandling |
| 2001 | Moving from mixed signal to RF test hardware development. John Ferrario, Randy Wolf, Hanyi Ding |
| 2001 | Multiple-output propagation transition fault test. Chao-Wen Tseng, Edward J. McCluskey |
| 2001 | Neighbor selection for variance reduction in I_DDQ and other parametric data. W. Robert Daasch, Kevin Cota, James McNames, Robert Madge |
| 2001 | OPMISR: the foundation for compressed ATPG vectors. Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko |
| 2001 | On RTL scan design. Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy |
| 2001 | On efficient error diagnosis of digital circuits. Nandini Sridhar, Michael S. Hsiao |
| 2001 | On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
| 2001 | On static test compaction and test pattern ordering for scan designs. Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | On-line testing and recovery in TMR systems for real-time applications. Shu-Yi Yu, Edward J. McCluskey |
| 2001 | On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. Cecilia Metra, Andrea Pagano, Bruno Riccò |
| 2001 | Optimal production test times through adaptive test programming. Scott Benner, Oluseyi Boroffice |
| 2001 | Pin electronics IC for high speed differential devices. Atsushi Oshima, John Poniatowski, Toshihiro Nomura |
| 2001 | Power supply transient signal integration circuit. Chintan Patel, Fidel Muradali, James F. Plusquellic |
| 2001 | Practical application of energy consumption ratio test. Eric Peterson, Wanli Jiang |
| 2001 | Practical, non-invasive optical probing for flip-chip devices. G. Dajee, Norman Goldblatt, Ted R. Lundquist, Steven Kasapi, Keneth R. Wilsher |
| 2001 | Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001 |
| 2001 | Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. Jörg E. Vollrath, Randall Rooney |
| 2001 | Ramp testing of ADC transition levels using finite resolution ramps. Solomon Max |
| 2001 | Rapid prototyping of time-based PDIT for substrate networks [MCM] . Aranggan Venkataratnam, Kimberly E. Newman |
| 2001 | Rapid-response temperature control provides new defect screening opportunities. Mark Malinoski, Burnell G. West |
| 2001 | Remote access to engineering test-a case study in providing engineering/diagnostic IC test services to Canadian universities. R. L. Stevenson, M. E. Jarosz, C. V. Verver |
| 2001 | Scan array solution for testing power and testing time. Lei Xu, Yihe Sun, Hongyi Chen |
| 2001 | Scan test sequencing hardware for structural test. Jamie Cullen |
| 2001 | Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107 Ken Tumin, Carmen Vargas, Ross Patterson, Chris Nappi |
| 2001 | Shadow write and read for at-speed BIST of TDM SRAMs. Yuejian Wu, Liviu Calin |
| 2001 | Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter |
| 2001 | Space and time compaction schemes for embedded cores. Ozgur Sinanoglu, Alex Orailoglu |
| 2001 | Split timing mode (STM)-answer to dual frequency domain testing. A. T. Sivaram |
| 2001 | Switch-level delay test of domino logic circuits. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. Nicola Nicolici, Bashir M. Al-Hashimi |
| 2001 | Tackling test trade-offs from design, manufacturing to market using economic modeling. Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff |
| 2001 | Tailoring ATPG for embedded testing. Rainer Dorsch, Hans-Joachim Wunderlich |
| 2001 | Terabit-per-second automated digital testing. David C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole |
| 2001 | Test and debug strategy of the PNX8525 Nexperia Bart Vermeulen, Steven Oostdijk, Frank Bouwman |
| 2001 | Test and repair of large embedded DRAMs. 2. Eric A. Nelson, Jeffrey H. Dreibelbis, Roderick McConnell |
| 2001 | Test and repair of large embedded DRAMs. I. Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis |
| 2001 | Test challenges for SONET/SDH physical layer OC3 devices and beyond. Udaya Natarajan |
| 2001 | Test cost reduction by at-speed BISR for embedded DRAMs. Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada |
| 2001 | Test evaluation and data on defect-oriented BIST architecture for high-speed PLL. Seongwon Kim, Mani Soma |
| 2001 | Test methodology for the McKinley processor. Don Douglas Josephson, Steve Poehlman, Vincent Govan, Clint Mumford |
| 2001 | Test path simulation and characterisation. Klaus Helmreich |
| 2001 | Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly |
| 2001 | Test vector encoding using partial LFSR reseeding. C. V. Krishna, Abhijit Jas, Nur A. Touba |
| 2001 | Test wrapper and test access mechanism co-optimization for system-on-chip. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2001 | Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. Christian Olgaard, Sule Ozev, Alex Orailoglu |
| 2001 | Tester retargetable patterns. Rohit Kapur, Thomas W. Williams |
| 2001 | Testing and programming flash memories on assemblies during high volume production. Frans G. M. de Jong, Alex S. Biewenga, D. C. L. (Erik) van Geest, T. F. Waayers |
| 2001 | Testing beyond EPA: TDF methodology solutions matrix. Sunil K. Jain, Greg P. Chema |
| 2001 | Testing clock distribution circuits using an analytic signal method. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida |
| 2001 | Testing for resistive opens and stuck opens. Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey |
| 2001 | Testing gigabit multilane SerDes interfaces with passive jitter injection filters. Bernd Laquai, Yi Cai |
| 2001 | Testing interconnects for noise and skew in gigahertz SoCs. Amir Attarha, Mehrdad Nourani |
| 2001 | Testing of critical paths for delay faults. Manish Sharma, Janak H. Patel |
| 2001 | The future of delta I_DDQ testing. Bram Kruseman, Rudger van Veen, Kees van Kaam |
| 2001 | Too much delay fault coverage is a bad thing. Jeff Rearick |
| 2001 | Towards a unified test process: from UML to end-of-line functional test. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei |
| 2001 | Two-dimensional test data compression for scan-based deterministic BIST. Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich |
| 2001 | Unit level predicted yield: a method of identifying high defect density die at wafer sort. Russell B. Miller, Walter C. Riordan |
| 2001 | Unsafe board states during PC-based boundary-scan testing. William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo |
| 2001 | Use of BIST in Sun Fire John Braden, Qing Lin, Brian Smith |
| 2001 | Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich |
| 2001 | When zero picoseconds edge placement accuracy is not enough. John Cheng |