| 2000 | : Reducing test application time in high-level test generation. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 2000 | A BIST approach for very deep sub-micron (VDSM) defects. Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo |
| 2000 | A built-in self-repair analyzer (CRESTA) for embedded DRAMs. Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka |
| 2000 | A comparison of classical scheduling approaches in power-constrained block-test scheduling. Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu |
| 2000 | A domain coverage metric for the validation of behavioral VHDL descriptions. Qiushuang Zhang, Ian G. Harris |
| 2000 | A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji |
| 2000 | A good excuse for reuse: "open" TAP controller design. David B. Lavo |
| 2000 | A mixed mode BIST scheme based on reseeding of folding counters. Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang |
| 2000 | A new paradigm in test for the next millennium. Jerry Katz, Rochit Rajsuman |
| 2000 | A programmable BIST architecture for clusters of multiple-port SRAMs. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni |
| 2000 | A scalable and efficient methodology to extract two node bridges from large industrial circuits. Sujit T. Zachariah, Sreejit Chakravarty |
| 2000 | A software development kit for dependable applications in embedded systems. Alfredo Benso, Silvia Chiusano, Paolo Prinetto |
| 2000 | A stand-alone integrated test core for time and frequency domain measurements. Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts |
| 2000 | Adapting scan architectures for low power operation. Lee Whetsel |
| 2000 | Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. Ramesh Karri, Kaijie Wu |
| 2000 | An ILP formulation to optimize test access mechanism in system-on-chip testing. Mehrdad Nourani, Christos A. Papachristou |
| 2000 | An analysis of the delay defect detection capability of the ECR test method. Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota |
| 2000 | An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory. Dieu Van Dinh, Virginia Rabitoy |
| 2000 | An empirical study on the effects of test type ordering on overall test efficiency. Jayashree Saxena, Kenneth M. Butler |
| 2000 | An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction. Kazuki Shigeta, Toshio Ishiyama |
| 2000 | Analysis of failure sources in surface-micromachined MEMS. Nilmoni Deb, Ronald D. Blanton |
| 2000 | Analysis of interconnect crosstalk defect coverage of test sets. Yi Zhao, Sujit Dey |
| 2000 | Application of deterministic logic BIST on industrial circuits. Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen |
| 2000 | BISTing data paths at behavioral level. David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
| 2000 | Bridging fault extraction from physical design data for manufacturing test development. Charles E. Stroud, John Marty Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic |
| 2000 | Bridging the gap between embedded test and ATE. Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras |
| 2000 | Case-based reasoning: diagnosis of faults in complex systems through reuse of experience. L. Derere |
| 2000 | Challenges of high supply currents during VLSI test. Gerald H. Johnson |
| 2000 | Combinational logic synthesis for diversity in duplex systems. Subhasish Mitra, Edward J. McCluskey |
| 2000 | Comparing functional and structural tests. Peter C. Maxwell, Ismed Hartanto, Lee Bentz |
| 2000 | Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler |
| 2000 | Concurrent error detection in block ciphers Santiago Fernández-Gomez, Juan J. Rodríguez-Andina, Enrique Mandado |
| 2000 | Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits. Steven F. Oakland |
| 2000 | Conversion of small functional test sets of nonscan blocks to scan patterns. Don E. Ross, Tim Wood, Grady Giles |
| 2000 | Current ratios: a self-scaling technique for production IDDQ testing. Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman |
| 2000 | DECOUPLE: defect current detection in deep submicron I_DDQ. Yukio Okuda |
| 2000 | DFT advances in Motorola's Next-Generation 74xx PowerPC Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan |
| 2000 | DIST-based detection and diagnosis of multiple faults in FPGAs. Miron Abramovici, Charles E. Stroud |
| 2000 | Deception by design: fooling ourselves with gate-level models. Peter C. Maxwell, Jeff Rearick |
| 2000 | Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors. Mike Rodgers |
| 2000 | Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? Will R. Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg |
| 2000 | Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton |
| 2000 | Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. Harold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy |
| 2000 | Deterministic partitioning techniques for fault diagnosis in scan-based BIST. Ismet Bayraktaroglu, Alex Orailoglu |
| 2000 | Device interfacing: the weakest link in the chain to break into the giga bit domain? Ulrich Schoettmer, Chris Wagner, Tom Bleakley |
| 2000 | Diagnostic test generation for sequential circuits. Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick |
| 2000 | Different experiments in test generation for XILINX FPGAs. Michel Renovell, Yervant Zorian |
| 2000 | Digital serial communication device testing and its implications on automatic test equipment architecture. Yongming Cai, T. P. Warwick, Sunil G. Rane, E. Masserrat |
| 2000 | Digital signature proposal for mixed-signal circuits. Anna Maria Brosa, Joan Figueras |
| 2000 | Doing it in STIL: intelligent conversion from STIL to an ATE format. Bruce R. Parnas |
| 2000 | Easy mixed signal test creation with test elements and procedures. Andy Kittross |
| 2000 | Efficient test mode selection and insertion for RTL-BIST. Subrata Roy, Gokhan Guner, Kwang-Ting Cheng |
| 2000 | End-to-end testing for boards and systems using boundary scan. Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace |
| 2000 | Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer |
| 2000 | Enhanced delay defect coverage with path-segments. Manish Sharma, Janak H. Patel |
| 2000 | Exploiting don't cares to enhance functional tests. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr |
| 2000 | Fault distinguishing pattern generation. Thomas Bartenstein |
| 2000 | HD Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian |
| 2000 | Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications. Cristo da Costa |
| 2000 | Identification of crosstalk switch failures in domino CMOS circuits. Rahul Kundu, Ronald D. Blanton |
| 2000 | Improving Delta-I_DDQ-based test methods. Claude Thibeault |
| 2000 | Increasing the IDDQ test resolution using current prediction. Pramodchandran N. Variyam |
| 2000 | Industrial evaluation of DRAM SIMM tests. Ad J. van de Goor, A. Paalvast |
| 2000 | It isn't just testing anymore (REDUX). Stephen F. Scheiber |
| 2000 | Jitter measurements of a PowerPC Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe |
| 2000 | Logic mapping on a microprocessor. Anjali Kinra, Hari Balachandran, Regy Thomas, John Carulli |
| 2000 | Low power BIST design by hypergraph partitioning: methodology and architectures. Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch |
| 2000 | MUST: multiple-stem analysis for identifying sequentially untestable faults. Qiang Peng, Miron Abramovici, Jacob Savir |
| 2000 | Measuring code edges of ADCs using interpolation and its application to offset and gain error testing. Pramodchandran N. Variyam, Vinay Agrawal |
| 2000 | Microwave test mismatch and power de-embedding. Peter M. Higgins, Jim Lampos |
| 2000 | Motherboard testing using the PCI bus. David McClintock, Lance Cunningham, Takis Petropoulos |
| 2000 | Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De |
| 2000 | Non-intrusive BIST for systems-on-a-chip. Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich |
| 2000 | Non-scan design for testability for synchronous sequential circuits based on conflict analysis. Dong Xiang, Yi Xu, Hideo Fujiwara |
| 2000 | Novel technique for built-in self-test of FPGA interconnects. Xiaoling Sun, Jian Xu, Ben Chan, Pieter M. Trouborst |
| 2000 | On invalidation mechanisms for non-robust delay tests. Haluk Konuk |
| 2000 | On using IEEE P1500 SECT for test plug-n-play. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur |
| 2000 | On validating data hold times for flip-flops in sequential circuits. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta |
| 2000 | On-line and off-line test of airborne digital systems: a reliability study. Jacob Savir |
| 2000 | On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores. Teresa L. McLaurin, John C. Potter |
| 2000 | Optical interferometric probing of advanced microprocessors. Travis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao |
| 2000 | Optimal INL/DNL testing of A/D converters using a linear model. Sasikumar Cherubal, Abhijit Chatterjee |
| 2000 | Optimal analog trim techniques for improving the linearity of pipeline ADCs. Turker Kuyel, Frank (Ching-Yuh) Tsay |
| 2000 | Optimization trade-offs for vector volume and test power. Bahram Pouya, Alfred L. Crouch |
| 2000 | Optimizing the flattened test-generation model for very large designs. Peter Wohl, John A. Waicukauski |
| 2000 | POIROT: a logic fault diagnosis tool and its applications. Srikanth Venkataraman, Scott Brady Drummonds |
| 2000 | Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. Pankaj Pant, Abhijit Chatterjee |
| 2000 | Pattern generation tools for the development of memory core test patterns for Rambus devices. John Privitera, Steven Woo, Craig Soldat |
| 2000 | Power conscious test synthesis and scheduling for BIST RTL data paths. Nicola Nicolici, Bashir M. Al-Hashimi |
| 2000 | Power pin testing: making the test coverage complete. Frans G. M. de Jong, Ben Kup, Rodger Schuttert |
| 2000 | Precise test generation for resistive bridging faults of CMOS combinational circuits. Toshiyuki Maeda, Kozo Kinoshita |
| 2000 | Predicting device performance from pass/fail transient signal analysis data. James F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel |
| 2000 | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 |
| 2000 | Programming of flash with ICT rights and responsibilities. Julia A. Keahey |
| 2000 | Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaning. Jerry J. Broz, James C. Andersen, Reynaldo M. Rincon |
| 2000 | Reducing test data volume using external/LBIST hybrid test patterns. Debaleena Das, Nur A. Touba |
| 2000 | Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
| 2000 | Selection of potentially testable path delay faults for test generation. Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Self test architecture for testing complex memory structures. Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor |
| 2000 | Si-emulation: system verification using simulation and emulation. Zan Yang, Byeong Min, Gwan Choi |
| 2000 | Static property checking using ATPG vs. BDD techniques. Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng |
| 2000 | Streamlining programmable device and system test using IEEE Std 1532. Neil G. Jacobson |
| 2000 | Structural test in a board self test environment. Ulf Pillkahn |
| 2000 | Stuck-fault tests vs. actual defects. Edward J. McCluskey, Chao-Wen Tseng |
| 2000 | Successful implementation of structured testing. Ronald A. Richmond |
| 2000 | System issues in boundary-scan board test. Kenneth P. Parker |
| 2000 | Technique for testing a very high speed mixed signal read channel design. Doug Matthes, John Ford |
| 2000 | Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor. Farideh Golshan |
| 2000 | Test generation for path-delay faults in one-dimensional iterative logic arrays. Nabil M. Abdulrazzaq, Sandeep K. Gupta |
| 2000 | Test method evaluation experiments and data. Phil Nigh, Anne E. Gattiker |
| 2000 | Test point insertion for compact test sets. M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor |
| 2000 | Test program synthesis for path delay faults in microprocessor cores. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
| 2000 | Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
| 2000 | Test structure verification of logical BIST: problems and solutions. Michael Cogswell, Don Pearl, James Sage, Alan Troidl |
| 2000 | Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. Jiun-Lang Huang, Kwang-Ting Cheng |
| 2000 | Testing for tunneling opens. Chien-Mo James Li, Edward J. McCluskey |
| 2000 | The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment. Stephen Harrison, Peter Collins, Greg Noeninckx |
| 2000 | The path to one-picosecond accuracy. Luca Sartori, Burnell G. West |
| 2000 | The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core. Teresa L. McLaurin, Frank Frederick |
| 2000 | Universal test generation using fault tuples. Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton |
| 2000 | Using on-chip test pattern compression for full scan SoC designs. Helmut Lang, Jens Pfeiffer, Jeff Maguire |
| 2000 | Variance reduction using wafer patterns in I_ddQ data. W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota |
| 2000 | Which concurrent error detection scheme to choose ? Subhasish Mitra, Edward J. McCluskey |
| 2000 | Wrapper design for embedded core test. Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel |