ITC A

166 papers

YearTitle / Authors
1999"DFY and DFR are more important than DFT".
David M. Wu
1999A DFT technique for high performance circuit testing.
Mansour Shashaani, Manoj Sachdev
1999A comparison of bridging fault simulation methods.
R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma
1999A design diversity metric and reliability analysis for redundant systems.
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
1999A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming.
Han Bin Kim, Dong Sam Ha
1999A method to improve the performance of high-speed waveform digitizing.
Koji Asami, Shinsuke Tajiri
1999A new approach to RF impedance test.
Dino Ren Tao
1999A new method for jitter decomposition through its distribution tail fitting.
Mike Peng Li, Jan B. Wilstrup, Ross Jessen, Dennis Petrich
1999A probe scheduling algorithm for MCM substrates.
Bruce C. Kim, Pinshan Jiang, Se Hyun Park
1999A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data.
Kenneth M. Butler
1999Accuracy requirements in at-speed functional test.
Burnell G. West
1999Accurate path delay fault coverage is feasible.
Spyros Tragoudas
1999Addressable test ports an approach to testing embedded cores.
Lee Whetsel
1999An accurate simulation model of the ATE test environment for very high speed devices.
Thomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner
1999An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.
Dilip K. Bhavsar
1999An efficient on-line-test and back-up scheme for embedded processors.
Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
1999An embedded technique for at-speed interconnect testing.
Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
1999An histogram based procedure for current testing of active defects.
Claude Thibeault
1999An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques.
Sandhya Seshadri, Michael S. Hsiao
1999An on-line BISTed SRAM IP core.
Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto
1999Analog Fault Simulation: Key to Product Quality, or a Foot in the Door.
Craig Force
1999Analog Fault Simulation: Need it? No. It is already done.
Eugene R. Atwood
1999Application of Tools Developed at the University of Iowa to ITC Benchmarks.
Sudhakar M. Reddy
1999Applications of semiconductor test economics, and multisite testing to lower cost of test.
Andrew C. Evans
1999Applying lessons learned from TDDB testing.
E. James Prendergast
1999At-speed structural test.
Burnell G. West
1999Auto-calibrating analog timer for on-chip testing.
Benoit Provost, Edgar Sánchez-Sinencio
1999Automatic Functional Test Generation - A Reality.
Raghuram S. Tapuri
1999Automatic timing margin failure location analysis by CycleStretch method.
Mitsuo Matsumoto, Yoshiharu Ikeda
1999BIST for phase-locked loops in digital applications.
Stephen K. Sunter, Aubin Roy
1999Benchmarking DAT with the ITC'99 ATPG Benchmarks.
Mario Konijnenburg, Hans van der Linden, Jeroen Geuzebroek
1999Breaking the complexity spiral in board test.
Stephen F. Scheiber
1999Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm.
Shigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani
1999Changing our Path to High Level ATPG.
Scott Davidson
1999Characterization and optimization of the production probing process.
Minh Quach, Rich Samuelson, David Shaw
1999Checking sequence generation for asynchronous sequential elements.
Sezer Gören, F. Joel Ferguson
1999Closing The Gap Between Process Development and Mixed Signal Design and Testing.
Hosam Haggag
1999Clustering based techniques for I_DDQ testing.
Sri Jandhyala, Hari Balachandran, Anura P. Jayasumana
1999Correlation of logical failures to a suspect process step.
Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith
1999Critical path identification and delay tests of dynamic circuits.
Kyung Tek Lee, Jacob A. Abraham
1999Current ratios: a self-scaling technique for production I_DDQ testing.
Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman
1999DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.
Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar
1999DFT is all I can afford, who cares about Design for Yield or Design for Reliability!
David M. Wu
1999DFT, DFY, DFR: Who Cares?
R. Scott Fetherston
1999DFT, DFY, and DFR; Which One(s) Do You Worry About?
James A. Monzel
1999DFT, test lifecycles and the product lifecycle.
Gordon D. Robinson
1999Defect detection using power supply transient signal analysis.
Amy Germida, Zheng Yan, James F. Plusquellic, Fidel Muradali
1999Delay fault testing of IP-based designs via symbolic path modeling.
HyungWon Kim, John P. Hayes
1999Delay testing considering power supply noise effects.
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
1999Delay testing of SOI circuits: Challenges with the history effect.
Eric W. MacDonald, Nur A. Touba
1999Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits.
Richard H. Livengood, Donna Medeiros
1999Design for In-System Programming.
David A. Bonnett
1999Design for Yield and Reliability is MORE Important Than DFT.
D. M. H. Walker
1999Design for test and time to market-friends or foes.
Jon Turino
1999Design for testability: it is time to deliver it for Time-to-Market.
Bulent I. Dervisoglu
1999Design of a test simulation environment for test program development.
J. J. O. Riordan
1999Design-for-test methodology for Motorola PowerPC microprocessors.
Magdy S. Abadir, Rajesh Raina
1999Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor.
Peilin Song, Franco Motika, Daniel R. Knebel, Rick Rizzolo, Mary P. Kusko, Julie Lee, Moyra K. McManus
1999Effective oscillation-based test for application to a DTMF filter bank.
Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas
1999Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis.
David B. Lavo, Tracy Larrabee, Jonathon E. Colburn
1999Embedded X86 testing methodology.
Luis Basto, Asif Khan, Pete Hodakievic
1999Estimating the integral non-linearity of A/D-converters via the frequency domain.
Nico Csizmadia, Augustus J. E. M. Janssen
1999Expediting ramp-to-volume production.
Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala
1999Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study.
David R. Lakin II, Adit D. Singh
1999Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato O. Forlenza, Ray Kurtulik, Wendy Chong
1999Fault diagnosis in scan-based BIST using both time and space information.
Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba
1999Fault modeling of suspended thermal MEMS.
Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois
1999Finite state machine synthesis with concurrent error detection.
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
1999Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test].
Tagashi Kitagaki
1999Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.
Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
1999HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.
Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
1999High Time For High Level ATPG.
Mahesh A. Iyer
1999High Time for Higher Level BIST.
Christos A. Papachristou
1999High level ATPG is important and is on its way!
Rohit Kapur
1999High level test bench generation using software engineering concepts.
Jean François Santucci, Christophe Paoli
1999High speed digital transceivers: A challenge for manufacturing.
Clifford B. Cole, Thomas P. Warwick
1999High time for high level ATPG.
Wu-Tung Cheng
1999High-level ATPG for Early Power Analysis.
Wolfgang Roethig
1999High-level ATPG: a real topic or an academic amusement?
Matteo Sonza Reorda
1999I
Anthony C. Miller
1999IMEMS accelerometer testing-test laboratory development and usage.
Richard W. Beegle, Robert W. Brocato, Ronald W. Grant
1999ITC'99 Benchmark Circuits - Preliminary Results.
Scott Davidson
1999Increasing Test Coverage in a VLSI Design Course.
Michael L. Bushnell
1999Increasing test coverage in a VLSI design course.
Michel Robert
1999Industrial evaluation of stress combinations for march tests applied to SRAMs.
Ad J. van de Goor, Ivo Schanstra
1999Interconnect delay fault testing with IEEE 1149.1.
Yuejian Wu, Paul Soong
1999Is Analog Fault Simulation a Key to Product Quality? Practical Considerations.
Bozena Kaminska
1999Is DFT right for you?
Jim Johnson
1999Is there a STIL for mixed signal testing?
Marc Loranger
1999It Makes Sense to Combine DFT and DFR/DFY.
Robert C. Aitken
1999LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.
Seongmoon Wang, Sandeep K. Gupta
1999Limited access testing of analog circuits: handling tolerances.
Cherif Ahrikencheikh, Michael Spears
1999Linearity testing issues of analog to digital converters.
Turker Kuyel
1999Logic BIST for large industrial designs: real issues and case studies.
Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
1999Low overhead test point insertion for scan-based BIST.
Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
1999Minimized power consumption for scan-based BIST.
Stefan Gerstendörfer, Hans-Joachim Wunderlich
1999Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.
Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
1999On achieving complete coverage of delay faults in full scan circuits using locally available lines.
Irith Pomeranz, Sudhakar M. Reddy
1999On-line fault detection in DSP circuits using extrapolated checksums with minimal test points.
Sudip Chakrabarti, Abhijit Chatterjee
1999Optimal conditions for Boolean and current detection of floating gate faults.
Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
1999Output in still, input in still.
Peter Wohl
1999PC manufacturing test in a high volume environment.
David Williams
1999Panel Statement: Increasing test coverage in a VLSI design course.
Mani Soma
1999Panel: Increasing test coverage in a VLSI desgin course.
Vishwani D. Agrawal
1999Particulate failures for surface-micromachined MEMS.
Tao Jiang, Ronald D. Blanton
1999Port interference faults in two-port memories.
Said Hamdioui, Ad J. van de Goor
1999Position Statement: Increasing Test Coverage in a VLSI Design Course.
Jacob A. Abraham
1999Position Statement: Testing in a VLSI Design Course.
Wayne H. Wolf
1999Practical optical waveform probing of flip-chip CMOS devices.
Keneth R. Wilsher, William K. Lo
1999Practical scan test generation and application for embedded FIFOs.
Jeff Rearick
1999Probe contact resistance variations during elevated temperature wafer test.
Jerry J. Broz, Reynaldo M. Rincon
1999Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999
1999RF (gigahertz) ATE production testing on wafer: options and tradeoffs.
Dean A. Gahagan
1999Relating linearity test results to design flaws of pipelined analog to digital converters.
Turker Kuyel, Haydar Bilhan
1999Resistive bridge fault modeling, simulation and test generation.
Vijay R. Sar-Dessai, D. M. H. Walker
1999Robust test methods applied to functional design verification.
Susana Stoica
1999Robust testability of primitive faults using test points.
Ramesh C. Tekumalla, Premachandran R. Menon
1999SCITT: Back to Basics in Mass Production Testing.
Frans G. M. de Jong
1999SCITT: Bringing DRAMs Into the Test Fold.
Frank W. Angelotti
1999SIA Roadmaps: Sunset Boulevard for l_DDQ.
Keith Baker
1999STAR-ATPG: a high speed test pattern generator for large scan designs.
Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
1999STIL: the device-oriented database for the test development lifecycle.
Nathan Biggs
1999Scan Insertion at the Behavioral Level.
Chouki Aktouf
1999Self-checking scheme for very fast clocks' skew correction.
Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò
1999Silicon debug: scan chains alone are not enough.
Gert-Jan van Rootselaar, Bart Vermeulen
1999Speed-up of high accuracy analog test stimulus optimization.
Abdelhakim Khouas, Anne Derieux
1999Static Component Interconnection Test Technology (SCITT).
Steffen Hellmold
1999Static component interconnect test technology (SCITT) a new technology for assembly testing.
Alex S. Biewenga, Henk D. L. Hollmann, Frans G. M. de Jong, Maurice Lousberg
1999Static component interconnection test technology in practice.
Frans G. M. de Jong, Rob Raaijmakers
1999Statistical threshold formulation for dynamic I_dd test.
Wanli Jiang, Bapiraju Vinnakota
1999Subband filtering scheme for analog and mixed-signal circuit testing.
Jeongjin Roh, Jacob A. Abraham
1999Switch-level delay test.
Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1999SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level.
Sitaran Yadavalli, Sudhakar M. Reddy
1999Synthesis of pattern generators based on cellular automata with phase shifters.
Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
1999System design verification tests - an overview.
Susana Stoica
1999Test features of a core-based co-processor array for video applications.
Jos van Beers, Harry Van Herten
1999Test generation for crosstalk-induced delay in integrated circuits.
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
1999Test process optimization: closing the gap in the defect spectrum.
Norma Barrett, Simon Martin, Chryssa Dislis
1999Test support processors for enhanced testability of high performance circuits.
David C. Keezer, Q. Zhou
1999Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.
Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring
1999Testability of the Philips 80C51 micro-controller.
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
1999Testing a system-on-a-chip with embedded microprocessor.
Rochit Rajsuman
1999Testing an MCM for high-energy physics experiments: a case study.
Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto
1999Testing high speed high accuracy analog to digital converters embedded in systems on a chip.
Solomon Max
1999Testing reusable IP-a case study.
Peter Harrod
1999The HASS development process.
David Rahe
1999The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA).
William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia N. Sanda, Steven C. Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky
1999The effects of test compaction on fault diagnosis.
Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
1999The evolution of a system test process [for Motorola GSM products].
Simon Martin, Robert Bleck, Chryssa Dislis, Des Farren
1999The integration of boundary-scan test methods to a mixed-signal environment.
Adam W. Ley
1999The test and debug features of the AMD-K7 microprocessor.
Timothy J. Wood
1999The test requirements model (TeRM) communicating test information throughout the product life cycle.
Lee A. Shombert, Danny C. Davis, Eric M. Bukata
1999The testability features of the 3rd generation ColdFire family of microprocessors.
Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran
1999The value of tester accuracy.
Wajih Dalal, Song Miao
1999Thin Gate Oxide Reliability.
Jeffrey L. Roehr
1999Towards a standard for embedded core test: an example.
Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
1999Towards a standardized procedure for automatic test equipment timing accuracy evaluation.
Yi Cai, William R. Ortner, C. T. Garrenton
1999Towards reducing "functional only" fails for the UltraSPARC microprocessors.
Anjali Kinra
1999Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
Li-C. Wang, Magdy S. Abadir
1999Transient current testing of 0.25 μm CMOS devices.
Bram Kruseman, Peter Janssen, Victor Zieren
1999Trends in SLI design and their effect on test.
Robert C. Aitken, Fidel Muradali
1999Using LSSD to test modules at the board level.
Thomas A. Ziaja
1999Using STIL to describe embedded core test requirements.
Brion L. Keller
1999Using Verilog simulation libraries for ATPG.
Peter Wohl, John A. Waicukauski
1999Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications.
Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
1999VLSI design 101 - The test module.
John Harrington