ITC A

161 papers

YearTitle / Authors
1998A BIST scheme for the detection of path-delay faults.
Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
1998A comprehensive approach to the partial scan problem using implicit state enumeration.
Priyank Kalla, Maciej J. Ciesielski
1998A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
Irith Pomeranz, Sudhakar M. Reddy
1998A distributed BIST technique for diagnosis of MCM interconnections.
Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
1998A fault injection environment for microprocessor-based boards.
Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1998A goal tree based high-level test planning system for DSP real number models.
Morris Lin, James R. Armstrong, F. Gail Gray
1998A high speed and area efficient on-chip analog waveform extractor.
Ara Hajjar, Gordon W. Roberts
1998A high throughput test methodology for MCM substrates.
Bruce C. Kim, David C. Keezer, Abhijit Chatterjee
1998A highly testable and diagnosable fabrication process test chip.
Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill
1998A layout-based approach for ordering scan chain flip-flops.
Samy Makar
1998A lifecycle approach to design validation is it necessary? Is it feasible?
Susana Stoica
1998A method of serial data jitter analysis using one-shot time interval measurements.
Jan B. Wilstrup
1998A new approach to scan chain reordering using physical design information.
Mokhtar Hirech, James Beausang, Xinli Gu
1998A new framework for generating optimal March tests for memory arrays.
Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
1998A new path-oriented effect-cause methodology to diagnose delay failures.
Yuan-Chieh Hsu, Sandeep K. Gupta
1998A non-enumerative path delay fault simulator for sequential circuits.
Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
1998A novel combinational testability analysis by considering signal correlation.
Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
1998A novel test methodology for core-based system LSIs and a testing time minimization problem.
Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
1998A performance analysis system for MEMS using automated imaging methods.
Glenn F. LaVigne, Sam L. Miller
1998A scalable architecture for VLSI test.
Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith
1998A structured and scalable mechanism for test access to embedded reusable cores.
Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters
1998A structured test re-use methodology for core-based system chips.
Prab Varma, Sandeep Bhatia
1998A test site thermal control system for at-speed manufacturing testing.
Mark Malinoski, James Maveety, Steve Knostman, Tom Jones
1998A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
1998ASIC jeopardy-diagnosing without a FAB.
Scott Davidson
1998ATPG in practical and non-traditional applications.
Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs
1998AVM
Bob Hickling
1998Accounting for the unexpected: fault diagnosis out of the ivory tower.
Brian Chess
1998Accumulator based deterministic BIST.
Rainer Dorsch, Hans-Joachim Wunderlich
1998Alternative interface methods for testing high speed bidirectional signals.
David C. Keezer, Q. Zhou
1998An algorithmic approach to optimizing fault coverage for BIST logic synthesis.
Srinivas Devadas, Kurt Keutzer
1998An almost full-scan BIST solution-higher fault coverage and shorter test application time.
Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng
1998An introduction to area array probing.
Frederick L. Taber
1998Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.
Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
1998Automated synthesis of large phase shifters for built-in self-test.
Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
1998BETSY: synthesizing circuits for a specified BIST environment.
Zhe Zhao, Bahram Pouya, Nur A. Touba
1998BIST vs. ATE for testing system-on-a-chip.
Neil Kelly
1998BIST vs. ATE: need a different vehicle?
Stephen K. Sunter
1998BIST: required for embedded DRAM.
Satoru Tanoi
1998Boundary scan BIST methodology for reconfigurable systems.
Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen
1998Built in self repair for embedded high density SRAM.
Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski
1998Built-in self-test of FPGA interconnect.
Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici
1998Buying time for the stuck-at fault model.
Jeff Rearick
1998CMOS IC reliability indicators and burn-in economics.
Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell
1998Cache RAM inductive fault analysis with fab defect modeling.
T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu
1998Can model-based and case-based expert systems operate together?
Moshe Ben-Bassat, Israel Beniaminy, David Joseph
1998Compact two-pattern test set generation for combinational and full scan circuits.
Ilker Hamzaoglu, Janak H. Patel
1998Consequences of port restrictions on testing two-port memories.
Said Hamdioui, Ad J. van de Goor
1998Contactless gigahertz testing.
Wolfgang Mertin, Anton Leyk, Ulf Behnke, Volker Wittpahl
1998Core test connectivity, communication, and control.
Lee Whetsel
1998Correlations between path delays and the accuracy of performance prediction.
Leendert M. Huisman
1998Cost of test reduction.
Hervé Deshayes
1998Current signatures: application [to CMOS].
Anne E. Gattiker, Wojciech Maly
1998DFT guidance through RTL test justification and propagation analysis.
Yiorgos Makris, Alex Orailoglu
1998Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.
Manoj Sachdev, Peter Janssen, Victor Zieren
1998Defect level prediction for I_DDQ testing.
Yukio Okuda, Isao Kubota, Masahiro Watanabe
1998Defect-oriented test quality assessment using fault sampling and simulation.
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
1998Defect-oriented testing of mixed-signal ICs: some industrial experience.
Y. Xing
1998Defining ATPG rules checking in STIL.
Peter Wohl, John A. Waicukauski
1998Delay test of chip I/Os using LSSD boundary scan.
Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur
1998Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core.
Craig Hunter, Justin Gaither
1998Design for diagnostics views and experiences.
Vallluri R. Rao
1998Design for soft-error robustness to rescue deep submicron scaling.
Michael Nicolaidis
1998Designing for scan test of high performance embedded memories.
E. Kofi Vida-Torku, George Joos
1998Detecting resistive shorts for CMOS domino circuits.
Jonathan T.-Y. Chang, Edward J. McCluskey
1998Detection of CMOS address decoder open faults with March and pseudo random memory tests.
Jan Otterstedt, Dirk Niggemeyer, T. W. Williams
1998Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.
Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
1998Deterministic BIST with multiple scan chains.
Gundolf Kiefer, Hans-Joachim Wunderlich
1998DfT and on-line test of high-performance data converters: a practical case.
Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas
1998Diagnosis and characterization of timing-related defects by time-dependent light emission.
Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika
1998Diagnosis method based on ΔIddq probabilistic signatures: experimental results.
Claude Thibeault, Luc Boisvert
1998Diagnostic techniques for the UltraSPARC microprocessors.
Anjali Kinra, Aswin Mehta, Neal Smith, Jackie Mitchell, Fred Valente
1998Digital bus faults measuring techniques.
Reuben Schrift
1998Digital oscillation-test method for delay and stuck-at fault testing of digital circuits.
Karim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska
1998Embedded self-testing checkers for low-cost arithmetic codes.
Steffen Tarnick, Albrecht P. Stroele
1998Enough is enough already.
William R. Simpson
1998Estimation of defect-free IDDQ in submicron circuits using switch level simulation.
Peter C. Maxwell, Jeff Rearick
1998Extracting gate-level networks from simulation tables.
Peter Wohl, John A. Waicukauski
1998Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Phil Nigh, David P. Vallett, Atul Patel, Jason Wright
1998Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems.
A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois
1998Failure modes for stiction in surface-micromachined MEMS.
Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla
1998FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.
Young-Jun Kwon, Ben Mathew, Hong Hao
1998Fine pitch (45 micron) P4 probing.
Toshinori Ishii, Hideaki Yoshida
1998Flying probe test systems: capabilities for effective testing.
Jack Ferguson
1998Functional ATE can meet the challenges.
Burnell G. West
1998GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.
Sandip Kundu
1998Generating interconnect models from prototype hardware.
Frank W. Angelotti
1998High quality, easy to use, on time ATE software Can it be done?
Dan Proskauer
1998High speed testing-have the laws of physics finally caught up with us?
Jerry Katz
1998High volume microprocessor test escapes, an analysis of defects our tests are missing.
Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong
1998High-coverage ATPG for datapath circuits with unimplemented blocks.
HyungWon Kim, John P. Hayes
1998How much testing is enough.
Susana Stoica
1998How real is the new SIA roadmap for mixed-signal test equipment?
William R. Ortner
1998How we test Siemens Embedded DRAM Cores.
Roderick McConnell, Udo Möller, Detlev Richter
1998IC diagnosis: preventing wars and war stories.
Jayashree Saxena
1998Implicit test generation for behavioral VHDL models.
Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
1998Improved sensitivity for parallel test of substrate interconnections.
David C. Keezer, K. E. Newman, John S. Davis
1998Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques.
Benoit Dufort, Gordon W. Roberts
1998Integrated probe card/interface solutions for specific test applications.
Jim Anderson
1998Just how real is the SIA roadmap.
Wayne M. Needham
1998Learning to knit SOCs profitably.
Todd E. Rockoff
1998Leveraging new standards in ATE software.
John Oonk
1998Limited access testing: IEEE 1149.4-instrumentation and methods.
John E. McDermid
1998MEMS fault model generation using CARAMEL.
Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton
1998Maximization of power dissipation under random excitation for burn-in testing.
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
1998Maximizing handler thermal throughput with a rib-roughened test tray.
Andreas C. Pfahnl, John H. Lienhard V, Alexander H. Slocum
1998Measuring jitter of high speed data channels using undersampling techniques.
Wajih Dalal, Daniel A. Rosenthal
1998Microelectromechanical systems (MEMS) tutorial.
Kaigham J. Gabriel
1998Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip.
Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott
1998Modeling the unknown! Towards model-independent fault and error diagnosis.
Vamsi Boppana, Masahiro Fujita
1998Modular logic built-in self-test for IP cores.
Janusz Rajski, Jerzy Tyszer
1998Multi-output one-digitizer measurement.
S. Sasho, M. Shibata
1998National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report.
Kwang-Ting Cheng
1998Native mode functional test generation for processors with applications to self test and design validation.
Jian Shen, Jacob A. Abraham
1998Novel optical probing technique for flip chip packaged microprocessors.
Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee
1998On applying non-classical defect models to automated diagnosis.
Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
1998On-chip versus off-chip test: an artificial dichotomy.
Robert C. Aitken
1998On-line detection of logic errors due to crosstalk, delay, and transient faults.
Cecilia Metra, Michele Favalli, Bruno Riccò
1998On-line testing of scalable signal processing architectures using a software test method.
Chouki Aktouf, Ghassan Al Hayek, Chantal Robach
1998Probabilistic mixed-model fault diagnosis.
David B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto
1998Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998
1998Process-tolerant test with energy consumption ratio.
Bapiraju Vinnakota, Wanli Jiang, Dechang Sun
1998Quad DCVS dynamic logic fault modeling and testing.
R. Dean Adams, Edmond S. Cooley, Patrick R. Hansen
1998R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique.
Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis
1998Reduction of errors due to source and meter in the nonlinearity test.
Luke S. L. Hsieh
1998SIA Roadmap: test must not limit future technologies.
Phil Nigh
1998SOC test: the devil is in the details of integration/implementation.
Kamalesh N. Ruparel
1998SRAM-based FPGA's: testing the LUT/RAM modules.
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998Scaling Deeper to Submicron: On-Line Testing to the Rescue.
Michael Nicolaidis
1998Scan chain design for test time reduction in core-based ICs.
Joep Aerts, Erik Jan Marinissen
1998Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.
Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen
1998Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.
Bulent I. Dervisoglu, Mike Ricchetti, William Eklow
1998Spice up your life: simulate mixed-signal ICs!
Keith Baker
1998Standard test interface language (STIL), extending the standard.
Tony Taylor
1998Static test sequence compaction based on segment reordering and accelerated vector restoration.
Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
1998Stimulus generation for built-in self-test of charge-pump phase-locked loops.
Benoît R. Veillette, Gordon W. Roberts
1998Stuck-at fault: a fault model for the next millennium.
Janak H. Patel
1998Switch-level bridging fault simulation in the presence of feedbacks.
Peter Dahlgren
1998System chip test: are we there yet?
Prab Varma
1998TAO: regular expression based high-level testability analysis and optimization.
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998Temperature control of a handler test interface.
Andreas C. Pfahnl, John H. Lienhard V, Alexander H. Slocum
1998Test generation in VLSI circuits for crosstalk noise.
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
1998Test methodology for a microprocessor with partial scan.
Leland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler
1998Test session oriented built-in self-testable data path synthesis.
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
1998Test vector decompression via cyclical scan chains and its application to testing core-based designs.
Abhijit Jas, Nur A. Touba
1998Test: when is enough enough?
Bret A. Stewart
1998Testability access of the high speed test features in the Alpha 21264 microprocessor.
Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson
1998Testing a multichip package for a consumer communications application.
Alex S. Biewenga, Math Muris, Rodger Schuttert, Urs Fawer
1998Testing embedded-core based system chips.
Yervant Zorian, Erik Jan Marinissen, Sujit Dey
1998Testing mixed signal SOCs.
Mark Burns
1998Testing the design: the evolution of test simulation.
Craig Force, Tom Austin
1998The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution.
Robert Gage, Ben Brown
1998The rise and fall of the ATE industry.
Todd E. Rockoff
1998The stuck-at fault: it ain't over 'til it's over.
Kenneth M. Butler
1998Toward understanding "Iddq-only" fails.
Anne E. Gattiker, Wojciech Maly
1998Towards an automatic diagnosis for high-level design validation.
Maisaa Khalil, Yves Le Traon, Chantal Robach
1998Triggering and clocking architecture for mixed signal test.
Naveed Zaman, Antony Spilman
1998Versatile BIST: an integrated approach to on-line/off-line BIST.
Ramesh Karri, Nilanjan Mukherjee
1998When "almost" is good enough: a fresh look at DSP clock rates.
Eric Rosenfeld, Solomon Max
1998When two worlds merge [test issues for system-level ICs].
Ken Lanier
1998probe card-a solution for at-speed, high density, wafer probing.
Rajiv Pandey, Dan Higgins