ITC A

139 papers

YearTitle / Authors
19971149.5: Now It's a Standard, So What?
Harry Hulvershorn
1997A 256Meg SDRAM BIST for Disturb Test Application.
Theo J. Powell, Dan Cline, Francis Hii
1997A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors.
Michael Mateja, Alfred L. Crouch, Renny Eisele, Grady Giles, Dale Amason
1997A DSP-Based Feedback Loop for Mixed-Signal VLSI Testing.
Lakshmikantha S. Prabhu, Daniel A. Rosenthal
1997A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates.
K. E. Newman, David C. Keezer
1997A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1997A New Probe Card Technology Using Compliant Microsprings
Nicholas Sporck
1997A New Validation Methodology Combining Test and Formal Verification for PowerPC
Li-C. Wang, Magdy S. Abadir
1997A Novel Functional Test Generation Method for Processors Using Commercial ATPG.
Raghuram S. Tupuri, Jacob A. Abraham
1997A Parameterized VHDL Library for On-Line Testing.
Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, Subhajit Roy, S. Wu
1997A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal.
R. Dean Adams, Edmond S. Cooley, Patrick R. Hansen
1997A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST.
Stephen K. Sunter, Naveena Nagi
1997A Simulation-Based JTAG ATPG Optimized for MCMs.
Andrew Flint
1997A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator.
Harbinder Singh, James Beausang, Girish Patankar
1997A Unified Interface for Scan Test Generation Based on STIL.
Peter Wohl, John A. Waicukauski
1997ACT: A DFT Tool for Self-Timed Circuits.
Ajay Khoche, Erik Brunvand
1997ASIC Manufacturing Test Cost Prediction at Early Design Stage.
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
1997Addressing Early Design-For-Test Synthesis in a Production Environment.
Vivek Chickermane, Kamran Zarrineh
1997Advances in Probe Technology: Best Sessions of the'97 Southwest Test Workshop.
Dave Unzicker, Michael Bonham, Rey Rincon
1997Algorithms for Switch Level Delay Fault Simulation.
Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
1997An Effective BIST Scheme for Arithmetic Logic Units.
Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis
1997An Efficient Method for Compressing Test Data.
Takahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha
1997An Efficient Scheme to Diagnose Scan Chains.
Sridhar Narayanan, Ashutosh Das
1997An IDDQ Sensor Circuit for Low-Voltage ICs.
Yukiya Miura
1997An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores.
Lee Whetsel
1997An On-Line Self-Testing Switched-Current Integrator.
Osama K. Abu-Shahla, Ian M. Bell
1997Analog AC Harmonic Method for Detecting Solder Opens.
Chuck Robinson
1997Analog Fault Diagnosis for Unpowered Circuit Boards.
Jiun-Lang Huang, Kwang-Ting Cheng
1997Analog and Mixed-Signal Benchmark Circuits-First Release.
Bozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, Bruce C. Kim, Adoración Rueda, Mani Soma, Prashant Goteti
1997Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.
Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
1997Analyzing a PowerPC
Richard Raimi, James Lear
1997Application and Analysis of IDDQ Diagnostic Software.
Phil Nigh, Donato O. Forlenza, Franco Motika
1997Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE)-A New Standard for System Diagnostics.
John W. Sheppard, Leslie A. Orlidge
1997BART: A Bridging Fault Test Generation for Sequential Circuits.
James P. Cusey, Janak H. Patel
1997BIST-Based Diagnostics of FPGA Logic Blocks.
Charles E. Stroud, Eric Lee, Miron Abramovici
1997Board Level Automated Fault Injection for Fault Coverage and Diagnostic Efficiency.
Bret A. Stewart
1997Bridging Fault Diagnosis in the Absence of Physical Information.
David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
1997Capacitive Leadframe Testing.
Ted T. Turner
1997Cell Signal Measurement for High-Density DRAMs.
Jörg E. Vollrath
1997Current Signatures: Application.
Anne E. Gattiker, Wojciech Maly
1997DS-LFSR: A New BIST TPG for Low Heat Dissipation.
Seongmoon Wang, Sandeep K. Gupta
1997Delay Testing with Clock Control: An Alternative to Enhanced Scan.
Ramesh C. Tekumalla, Premachandran R. Menon
1997Design and Realization of an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and I
Karim Arabi, Bozena Kaminska
1997Design for Primitive Delay Fault Testability.
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
1997Design of Cache Test Hardware on the HP PA8500.
Jeff Brauch, Jay Fleischman
1997Design, Fabrications and Use of Mixed-Signal IC Testability Structures.
Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa
1997Development of a MEMS Testing Methodology.
Abhijeet Kolpekwar, Ronald D. Blanton
1997Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing.
Srikanth Venkataraman, W. Kent Fuchs
1997Dynamic Testing of ADCs Using Wavelet Transforms.
Takahiro J. Yamaguchi, Mani Soma
1997Effective Path Selection for Delay Fault Testing of Sequential Circuits.
Tapan J. Chakraborty, Vishwani D. Agrawal
1997Efficient Identification of Non-Robustly Untestable Path Delay Faults.
Zhongcheng Li, Robert K. Brayton, Yinghua Min
1997Embedded At-Speed Test Probe.
Mitch Aigner
1997Embedded Core Test Plug-n-Play: Is It Achievable?
Rudy Garcia
1997Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis.
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
1997Ethics, Professionalism and Accountability in Testing.
William R. Simpson
1997Experiences with Implementation of I
Ralf Arnold, Markus Feuser, Horst-Udo Wedekind, Thorsten Bode
1997Experimental Results for Current-Based Analog Scan.
Thomas M. Bocek, Tuyen D. Vu, Mani Soma, Jason D. Moffatt
1997Fault Diagnosis in Scan-Based BIST.
Janusz Rajski, Jerzy Tyszer
1997Fault Macromodeling for Analog/Mixed-Signal Circuits.
Chen-Yang Pan, Kwang-Ting Cheng
1997Fault Model Extension for Diagnosing Custom Cell Fails.
Gilbert Vandling, Thomas Bartenstein
1997Finding Opens with Optics.
Douglas W. Raymond
1997Future Management of the Semiconductor Manufacturing Process.
James T. Healy
1997H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs.
Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey
1997HABIST: Histogram-Based Analog Built-In Self-Test.
Arnold Frisch, Thomas Almy
1997Hardware Compression Speeds on Bitmap Fail Display.
Robert Gage, Ben Brown, John Donaldson, Alexander Joffe
1997Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis.
Ramakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao
1997High-Performance Production Test Contractors for Fine-Pitch Integrated Circuits.
James J. Brandes
1997How Seriously Do You Take Your Possible-Detect Faults?
Rajesh Raina, Charles Njinda, Robert F. Molyneaux
1997I
Antoni Ferré, Joan Figueras
1997IC Diagnosis: Industry Issues.
Jerry M. Soden, Christopher L. Henderson
1997IEEE P1149.4-Almost a Standard.
Adam Cron
1997Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
1997Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure.
José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves
1997Incorporating Physical Design-for-Test into Routing.
Richard McGowen, F. Joel Ferguson
1997Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs.
Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
1997Logic Diagnosis-Diversion or Necessity?
W. Kent Fuchs
1997Logical Diagnosis Solutions Must Drive Yield Improvement.
Paul G. Ryan
1997Low Current and Low Voltages-The High-End OP AMP Testing Challenge.
Bob Cometta, Jan Witte
1997Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test.
David C. Keezer, R. J. Wenzel
1997Manufacturing Pattern Development for the Alpha 21164 Microprocessor.
Carol Stolicny, Richard Davies, Pamela McKernan, Tuyen Truong
1997Memory Test-Debugging Test Vectors Without ATE.
Steve Westfall
1997Modifying User-Defined Logic for Test Access to Embedded Cores.
Bahram Pouya, Nur A. Touba
1997Next-Generation PowerPC
Carol Pyron, Javier Prado, James Golab
1997OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test Programs.
Yuhai Ma, Wanchun Shi
1997On Using Machine Learning for Logic BIST.
Christophe Fagot, Patrick Girard, Christian Landrault
1997On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops.
Benoît R. Veillette, Gordon W. Roberts
1997On-Line Testable Logic Desgin for FPGA Implementation.
Alfred L. Burress, Parag K. Lala
1997On-Line Testing Scheme for Clock's Faults.
Cecilia Metra, Michele Favalli, Bruno Riccò
1997On-Line Testing for VLSI.
Michael Nicolaidis
1997Optical Communication Channel Test Using BIST Approaches.
Mathieu Gagnon, Bozena Kaminska
1997Oscillation Built-In Self Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits.
Karim Arabi, Bozena Kaminska
1997Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits.
Haluk Konuk, F. Joel Ferguson
1997P1149.4-Problem or Solution for Mixed-Signal IC Design?
Stephen K. Sunter
1997Parameterizable Testing Scheme for FIR Filters.
Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
1997Pentium
Adrian Carbine, Derek Feltham
1997Pin Margin Analysis.
Robert E. Huston
1997Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't).
Colin M. Maunder
1997Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997
1997Putting the Squeeze on Test Sequences.
Elizabeth M. Rudnick, Janak H. Patel
1997RF Introduction and Analog Junction Techniques for Finding Opens.
B. Karen McElfresh
1997Real-Time In-situ Monitoring and Characterization of Production Wafer Probing Process.
Minh Quach, Kim Harper
1997Scan Latch Design for Delay Test.
Jacob Savir
1997Scan Synthesis for One-Hot Signals.
Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
1997Scan-Encoded Test Pattern Generation for BIST.
Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
1997Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study.
Adit D. Singh, Phil Nigh, C. Mani Krishna
1997Sequential Test Generation with Advanced Illegal State Search.
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
1997Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams.
Benoit Dufort, Gordon W. Roberts
1997Signature Analysis for IC Diagnosis and Failure Analysis.
Christopher L. Henderson, Jerry M. Soden
1997So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.
Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
1997Solder Paste Inspection: Process Control for Defect Reduction.
Donald Burr
1997Structuring STIL for Incremental Test Development.
Gregory A. Maston
1997Supervisors for Testing Non-Deterministically Specified Systems.
Tony Savor, Rudolph E. Seviora
1997System-Level Boundary-Scan in a Highly Integrated Switch.
William J. Hughes III
1997Test Access of TAP'ed & Non-TAP'ed Cores.
Lee Whetsel
1997Test Requirements for Embedded Core-Based Systems and IEEE P1500.
Yervant Zorian
1997Test Strategy Sensitivity to Defect Parameters.
Michel Renovell, Yves Bertrand
1997Test Width Compression for Built-In Self Testing.
Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray
1997Testability Analysis and ATPG on Behavioral RT-Level VHDL.
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1997Testability Enhancement for Behavioral Descriptions Containing Conditional Statements.
Kelly A. Ockunzzi, Christos A. Papachristou
1997Testability Features of AMD-K6
R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma
1997Testing the 400-MHz IBM Generation-4 CMOS Chip.
Thomas G. Foote, Dale E. Hoffman, William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko
1997Testing the Enterprise IBM System/390
Otto A. Torreiter, Ulrich Baur, Georg Goecke, Kevin Melocco
1997The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices.
Yeoh Eng Hong, Martin Tay Tiong We
1997The Case of Partial Scan.
Jeff Rearick
1997The Fail-Stop Controller AE11.
Eberhard Böhl, Thomas Lindenkreuz, R. Stephan
1997The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers.
Ad J. van de Goor, Mike Lin
1997The Search for the Universal Probe Card Solution.
R. Dennis Bates
1997Thoughts on Core Integration and Test.
Thomas L. Anderson
1997To DFT or Not to DFT?
Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
1997Transient Power Supply Voltage (V
Edward I. Cole Jr., Jerry M. Soden, Paiboon Tangyunyong, Patrick L. Candelaria, Richard W. Beegle, Daniel L. Barton, Christopher L. Henderson, Charles F. Hawkins
1997Tree-Structured Linear Cellular Automata and Their Applications as PRPGs.
J. Li, X. Sun, K. Soon
1997Unpowered Opens Test with X-Ray Laminography.
Stig Oresjo
1997Using BIST Control for Pattern Generation.
Gundolf Kiefer, Hans-Joachim Wunderlich
1997Vision Inspection: Meeting the Promise?
Richard Pye
1997Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique.
Anne Meixner, Jash Banik
1997Why Automate Optical Inspection?
Douglas W. Raymond, Dominic F. Haigh
1997Why Would an ASIC Foundry Accept Anything Less than Full Scan?
Steven F. Oakland
1997i
J. S. Beasley, S. Pour-Mozafari, D. Huggett, Alan W. Righter, C. J. Apodaca