| 1996 | A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. Hugo Cheung, Sandeep K. Gupta |
| 1996 | A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe |
| 1996 | A Demonstration IC for the P1149.4 Mixed-Signal Test Standard. Keith Lofstrom |
| 1996 | A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
| 1996 | A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. Dong Xiang, Janak H. Patel |
| 1996 | A Method of Extending an 1149.1 Bus for Mixed-Signal Testing. Robert J. Russell |
| 1996 | A Novel Approach to the Analysis of VLSI Device Test Programs. Yuhai Ma, Wanchun Shi |
| 1996 | A Roadmap for Boundary-Scan Test Reuse. D. Eugene Wedge, Tom Conner |
| 1996 | A Unified Framework for Design Validation and Manufacturing Test. Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote |
| 1996 | A Unifying Methodology for Intellectual Property and Custom Logic Testing. Sandeep Bhatia, Tushar Gheewala, Prab Varma |
| 1996 | A Unique Methodology for At-Speed Test of cDSP David Potts, Roger Griesmer |
| 1996 | A Universal Technique for Accelerating Simulation of Scan Test Patterns. Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski |
| 1996 | ASIC BIST Synthesis: A VHDL Approach. Tom Eberle, Robert McVay, Chris Meyers, Jason Moore |
| 1996 | ASIC Yield Estimation at Early Design Cycle. Von-Kyoung Kim, Mick Tegethoff, Tom Chen |
| 1996 | ATPD: An Automatic Test Pattern Generator for Path Delay Faults. Dimitrios Karayiannis, Spyros Tragoudas |
| 1996 | Accelerated Compact Test Set Generation for Three-State Circuits. M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor |
| 1996 | Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. Nur A. Touba, Edward J. McCluskey |
| 1996 | An ATPG-Based Framework for Verifying Sequential Equivalence. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser |
| 1996 | An Application of Photoconductive Switch for High-Speed Testing. Kazunori Chihara, Takashi Sekino, Koji Sasaki |
| 1996 | An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention. Volker Schöber, Thomas Kiel |
| 1996 | An Effective BIST Scheme for Datapaths. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
| 1996 | An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | An Integration of Memory-Based Analog Signal Generation into Current DFT Architectures. Evan M. Hawrysh, Gordon W. Roberts |
| 1996 | An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics. David P. Vallett |
| 1996 | Analog AC Harmonic Method for Detecting Solder Opens. Anthony J. Suto |
| 1996 | Analog/Digital Testing of Loaded Boards Without Dedicated Test Points. Christophe Vaucher, Louis Balme |
| 1996 | Analysis and Detection of Timing Failures in an Experimental Test Chip. Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell |
| 1996 | Application of Boundary Scan in a Fault Tolerant Computer System. Matthew Boutin, Peter Dziel |
| 1996 | Asynchronous Design: Working the Fast Lane. Marly Roncken |
| 1996 | BIST Fault Diagnosis in Scan-Based VLSI Environments. Yuejian Wu, Saman Adham |
| 1996 | Backplane Interconnect Test in a Boundary-Scan Environment. Wuudiann Ke |
| 1996 | Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis. David B. Lavo, Tracy Larrabee, Brian Chess |
| 1996 | Burn-in Elimination of a High Volume Microprocessor Using I Timothy R. Henry, Thomas Soo |
| 1996 | Capacitive Leadframe Testing. Ted T. Turner |
| 1996 | Challenge of the 90's: Testing CoreWare Rochit Rajsuman |
| 1996 | Commercial Design Verification: Methodology and Tools. Carl Pixley, Noel R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen |
| 1996 | Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
| 1996 | Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. Nagesh Tamarapalli, Janusz Rajski |
| 1996 | Correlating Defects to Functional and I Theo J. Powell, James R. Pair, Bernard G. Carbajal III |
| 1996 | Cost Effective Frequency Measurement for Production Testing. Ralf Stoffels |
| 1996 | DFT Strategy for Intel Microprocessors. Wayne M. Needham, Naga Gollakota |
| 1996 | Deep Sub-micron I Manoj Sachdev |
| 1996 | Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira |
| 1996 | Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs. Thomas Olbrich, Jordi Pérez, Ian Andrew Grout, Andrew Mark David Richardson, Carles Ferrer |
| 1996 | Detecting Delay Flaws by Very-Low-Voltage Testing. Jonathan T.-Y. Chang, Edward J. McCluskey |
| 1996 | Developing a Testing Maturity Model for Software Test Process Evaluation and Improvement. Ilene Burnstein, Taratip Suwannasart, C. Robert Carlson |
| 1996 | Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs |
| 1996 | Digital Integrated Circuit Testing using Transient Signal Analysis. James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan |
| 1996 | Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham |
| 1996 | Early Capture for Boundary Scan Timing Measurements. Keith Lofstrom |
| 1996 | Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. Hiromu Fujioka, Koji Nakamae, Akio Higashi |
| 1996 | Emerging Technologies Drive Domain-Specific Solutions. Walden C. Rhines |
| 1996 | Extending Calibration Intervals. Solomon Max |
| 1996 | Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. Yuyun Liao, D. M. H. Walker |
| 1996 | Formal Verification of the UltraSPARC Marc E. Levitt |
| 1996 | Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card. Seiji Sasho, Teruhisa Sakata |
| 1996 | From Specification Validation to Hardware Testing: A Unified Method. Ghassan Al Hayek, Chantal Robach |
| 1996 | Generation Technique of 500MHz Ultra-High Speed Algorithmic Pattern. Hideaki Imada, Kenichi Fujisaki, Toshimi Ohsawa, Masaru Tsuto |
| 1996 | Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li |
| 1996 | Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs. Giri Devarayanadurg, Prashant Goteti, Mani Soma |
| 1996 | High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors. Jack Ferguson |
| 1996 | High Resolution I Alan W. Righter, Jerry M. Soden, Richard W. Beegle |
| 1996 | High-Speed I Kenji Isawa, Yoshihiro Hashimoto |
| 1996 | I Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly |
| 1996 | I Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown |
| 1996 | IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science. Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson |
| 1996 | Identification and Test Generation for Primitive Faults. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar |
| 1996 | Improving Gate Level Fault Coverage by RTL Fault Grading. Weiwei Mao, Ravi K. Gulati |
| 1996 | Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena |
| 1996 | Integrating Scan into Hierarchical Synthesis Methodologies. James Beausang, Chris Ellingham, Markus Robinson |
| 1996 | Introduction ITC 1996 Lecture Series on Unpowered Opens Testing. Kenneth P. Parker |
| 1996 | Issues in Optimizing the Test Process - A Telecom Case Study. Felix Frayman, Mick Tegethoff, Brenton White |
| 1996 | LFSR Reseeding as a Component of Board Level BIST. Pieter M. Trouborst |
| 1996 | LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits. Naim Ben-Hamida, Khaled Saab, David Marche, Bozena Kaminska, Guy Quesnel |
| 1996 | Local Transformations and Robust Dependent Path Delay. Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy |
| 1996 | MCM Compute Node Thermal Failure - Design or Test Problem? Edward P. Sayre |
| 1996 | MFBIST: A BIST Method for Random Pattern Resistant Circuits. Mohammed F. AlShaibi, Charles R. Kime |
| 1996 | Manufacturing Test of Fiber Channel Communications Cards and Optical Subassemblies. Steven DeFoster, Dennis Karst, Matthew Peterson, Paul Sendelbach, Kirk Kottschade |
| 1996 | Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig |
| 1996 | Modelling the Unmodellable: Algorithmic Fault Diagnosis. Robert C. Aitken |
| 1996 | New and Not-So-New Test Challenges of the Next Decade. Wojciech Maly |
| 1996 | Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits. Kazuyuki Ozaki, Hidenori Sekiguchi, Shinichi Wakana, Yoshiro Goto, Yasutoshi Umehara, Jun Matsumoto |
| 1996 | On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | On Potential Fault Detection in Sequential Circuits. Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz |
| 1996 | Opens Board Test Coverage: When is 99% Really 40%? Mick Tegethoff, Kenneth P. Parker, Ken Lee |
| 1996 | Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian |
| 1996 | Optimal Scan for Pipelined Testing: An Asynchronous Foundation. Marly Roncken, Emile H. L. Aarts, Wim F. J. Verhaegh |
| 1996 | Orthogonal Scan: Low-Overhead Scan for Data Paths. Robert B. Norwood, Edward J. McCluskey |
| 1996 | Partial Scan Design Based on State Transition Modeling. Vamsi Boppana, W. Kent Fuchs |
| 1996 | Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
| 1996 | PowerPC Neeta Ganguly, Magdy S. Abadir, Manish Pandey |
| 1996 | Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment. Donald Staab |
| 1996 | Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996 |
| 1996 | Process-Aggravated Noise (PAN): New Validation and Test Problems. Melvin A. Breuer, Sandeep K. Gupta |
| 1996 | Proposal to Simplify Development of a Mixed-Signal Test Standard. Lee Whetsel |
| 1996 | Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits. Michael J. Ohletz |
| 1996 | Risk Assessment Sampling Plans for Non-Standard (Maverick) Material. Daniel P. Core |
| 1996 | SPC on the IC-Production Test Process. Jos van der Peet, Ger van Boxem |
| 1996 | Scan Design Oriented Test Technique for VLSI's Using ATE. Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima |
| 1996 | Self-Learning Signature Analysis for Non-Volatile Memory Testing. Piero Olivo, Marcello Dalpasso |
| 1996 | Shmoo Plots - the Black Art of IC Test. Keith Baker, Jos van Beers |
| 1996 | Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms. Anthony Taylor, Gregory A. Maston |
| 1996 | Synthesis of Self-Testing Finite State Machines from High-Level Specifications. Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani |
| 1996 | Synthesis-for-Initializability of Asynchronous Sequential Machines. Montek Singh, Steven M. Nowick |
| 1996 | System Level Fault Simulation. Pablo Sanchez, Isabel Hidalgo |
| 1996 | Test Generation for Global Delay Faults. G. M. Luong, D. M. H. Walker |
| 1996 | Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. Peter Wohl, John A. Waicukauski |
| 1996 | Test Pattern Generation for Circuits with Asynchronous Signals Based on Scan. Mitsuo Teramoto, Tomoo Fukazawa |
| 1996 | Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation. Marly Roncken, Eric Bruls |
| 1996 | Testability Features for a Submicron Voice-coder ASIC. Francis Pichon |
| 1996 | Testability-Oriented Hardware/Software Partitioning. Yves Le Traon, Ghassan Al Hayek, Chantal Robach |
| 1996 | Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE System. Barry D. Kulp |
| 1996 | Testing the Digital Modulation of PHS Devices. Koji Asami |
| 1996 | Testing-Based Analysis of Real-Time System Models. Duncan Clarke, Insup Lee |
| 1996 | The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test Systems. Michael G. Davis |
| 1996 | The Key to Concurrent Engineering is Design Tools. William R. Simpson |
| 1996 | The Need for Complete System Level Test Standardization. Peter Dziel |
| 1996 | The Return of Asynchronous Logic. Stephen B. Furber |
| 1996 | Three Different MCMs, Three Different Test Strategies. Andrew Flint |
| 1996 | Towards an Effective I Jos van Sas, Urbain Swerts, Marc Darquennes |
| 1996 | Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test. Joe Wrinn |
| 1996 | Two-Dimensional Test Data Decompressor for Multiple Scan Designs. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski |
| 1996 | Unpowered Opens Test with X-Ray Laminography. Stig Oresjo |
| 1996 | Using ILA Testing for BIST in FPGAs. Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici |
| 1996 | Using Target Faults To Detect Non-Tartget Defects. Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1996 | Virtual Test of Noise and Jitter Parameters. Klaus Helmreich, G. Reinwardt |
| 1996 | Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. Anne Meixner, Jash Banik |