ITC A

137 papers

YearTitle / Authors
1993"In System" Transparent Autodiagnostics of Rams.
Janusz Sosnowski
1993A BIST Scheme for an SNR Test of a Sigma-Delta ADC.
Michael F. Toner, Gordon W. Roberts
1993A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.
Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda
1993A Comparison of Stuck-At Fault Coverage and I
Paul C. Wiscombe
1993A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths.
Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf
1993A Flexible Approach to Data Collection for Component Test Systems.
Jim Mosley III
1993A General Purpose I
Kenneth M. Wallquist, Alan W. Righter, Charles F. Hawkins
1993A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.
Irith Pomeranz, Sudhakar M. Reddy
1993A Method for Delay Fault Self-Testing of Macrocells.
Harold N. Scholz, Duane R. Aadsen, Yervant Zorian
1993A Method for Reducing the Search Space in Test Pattern Generation.
Mitsuo Teramoto
1993A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
Jayashree Saxena, Dhiraj K. Pradhan
1993A New Approach for PLL Characterization on Mixed Signal ATE.
Shinichi Kimura, Makoto Kimura, Takayuki Nakatani, Masao Sugai
1993A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems.
Richard K. Feldman
1993A Serial-Scan Test-Vector-Compression Methodology.
Chauchin Su, Kychin Hwang
1993A Synthesis Approach to Design for Testability.
Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1993A Test Methodology for VLSI Chips on Silicon.
Thomas M. Storey
1993A Universal Framework for Managed Built-in Test.
Colin M. Maunder
1993Algorithms for Cost Optimised Test Strategy Selection.
Chryssa Dislis, J. H. Dick, Anthony P. Ambler
1993An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test.
James Broseghini, Donald H. Lenhert
1993An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1993Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling.
Naim Ben-Hamida, Bozena Kaminska
1993Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs.
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
1993Application of Statistical Techniques to Critical System Parameters.
Rick Boyle, Jack Donovan, Eugene R. Hnatek, Alex M. Ijaz
1993Automated Testing of Open Software Standards.
James F. Leathrum, K. A. Liburdy
1993Automated Wafer Lot Approval: A Statistically Based Implementation.
Kurt A. Milne
1993Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.
Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa
1993Automotive Industry: The Next DFT Challenge.
Michael S. Ledford
1993BIST and Delay Fault Detection.
Slawomir Pilarski, Alicja Pierzynska
1993BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution.
José Manuel Martins Ferreira, Manuel G. Gericota, José L. Ramalho, Gustavo R. Alves
1993BIST for Embedded Static RAMs with Coverage Calculation.
Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey
1993BP-1992 A Comparison of Defect Models for Fault Location with I
Robert C. Aitken
1993Benefits of Boundary-Scan to In-Circuit Test.
David A. Greene
1993Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic.
Peter C. Maxwell, Robert C. Aitken
1993Built-In Current Sensor for I
Ching-Wen Hsue, Chih-Jen Lin
1993CAD-Driven High-Precision E-Beam Positioning.
Kent Kwang, Hsin Wang, Arthur Hu, Mitsuyuki Asaki, Hironobu Niijima
1993CHEETA: Composition of Hierarchical Sequential Tests Using ATKET.
Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab
1993CMOS Bridges and Resistive Transistor Faults: I
Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser
1993Calculatoin of Multiple Sets of Weights for Weighted-Random Testing.
Michael Bershteyn
1993Catch the Ground Bounce Before It Hits your System.
E. Kurzweil, M. Lallement, R. Blanc, R. Pasquinelli
1993Certification Trails and Software Design for Testability.
Gregory F. Sullivan, Dwight S. Wilson, Gerald M. Masson
1993Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics.
Will Creek
1993Control and Observation of Analog Nodes in Mixed-Signal Boards.
José Silva Matos, Ana C. Leão, João Canas Ferreira
1993Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development.
Tom Austin
1993Cultural Evolution in Software Testing.
Alex Elentukh
1993DELTEST: Deterministic Test Generation for Gate-Delay Faults.
Udo Mahlstedt
1993DFT: Profit or Loss -- A Position Paper.
Jon Turino
1993DOs and DON'Ts in Computing Fault Coverage.
Miron Abramovici
1993Delay Testing Using a Matrix of Accessible Storage.
Prab Varma, Tushar Gheewala
1993Delay Testing for Non-Robust Untestable Circuits.
Kwang-Ting Cheng, Hsi-Chuan Chen
1993Design and Test: What Will It Take to Tie the Knot?
Joseph B. Costello
1993Design for Testability of a Modular, Mixed Signal Family of VLSI Devices.
Ed Flaherty, Andrew Allen, John Morris
1993Design of Scan-Based Path-Delay-Testable Sequential Circuits.
Ankan K. Pramanick, Sandip Kundu
1993Design-For-Test Techniques Utilized in an Avionics Computer MCM.
Russell J. Wagner, Joel A. Jorgenson
1993Design-For-Testability Economics.
Carl W. Thatcher
1993Development of Fault Model and Test Algorithms for Embedded DRAMs.
Manoj Sachdev, Math Verstraelen
1993Differential Virtual Instrumentation with Continuously.
Bryan J. Dinteman, Paul Botsford
1993Distributed Implementation of an ATPG System Using Dynamic Fault Allocation.
Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio
1993Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards.
Chryssa Dislis, J. H. Dick, I. D. Dear, I. N. Azu, Anthony P. Ambler
1993Efficient Testing of Software Modifications.
Anneliese von Mayrhauser, Kurt M. Olender
1993Experience in Diagnosing a Remote, Tele-Controlled Unit Using the AITEST Expert System.
Israel Beniaminy, Moshe Ben-Bassat, M. Bodenheimer, M. Eshel
1993Extraction of Coupled SPICE Models for Packages and Interconnects.
Scott Diamond, Bo Janko
1993FFT Based Troubleshooting of 120dB Dynamic Range ADC Systems.
David Ownby, Harold Bogard
1993Fast and Accurate CMOS Bridging Fault Simulation.
Jeff Rearick, Janak H. Patel
1993Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers.
Mani Soma
1993Fault Diagnosis of Flash ADC using DNL Test.
Anchada Charoenrook, Mani Soma
1993Fault Location Algorithms for Repairable Embedded.
Robert P. Treuer, Vinod K. Agarwal
1993Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs.
John O'Donnell
1993Generation of Compact Delay Tests by Multiple-Path Activation.
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test.
Miguel Miranda, Carlos A. López-Barrio
1993Hierarchically Accessing 1149.1 Applications in a System Environment.
Lee Whetsel
1993High-Speed Sampling Capability for a VLSI Mixed-Signal Tester.
Paul Sakamoto, Tom Chiu
1993IEEE 1149 Standards - Changing Testing, Silicon to Systems.
Rodham E. Tulloss
1993IEEE 1149.1 Growing Pains.
Wayne T. Daniel
1993IEEE 1149.1: How to Justify Implementation.
Mick Tegethoff
1993IEEE P1149.5 to 1149.1 Data and Protocol Conversion.
Christopher Poirier
1993IRIDIUM
Cary Champlin
1993Implementation of Parallelsite Test on an 8Bit Configurable Microcontroller.
Douglas J. Mirizzi, Willie Jerrels, Dale Ohmart
1993Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation.
Danial J. Neebel, Charles R. Kime
1993Integrating Electrical Test into Final Assembly.
Hugh Littlebury, Roger Brueckner
1993Keep Alive - A New Requirement for High Performance uProcessor Test.
Rudy Garcia
1993Knowledge-Based Testing.
Himanshu Kumar, Scott A. Erjavic
1993Known Godd Die for MCMs: Enabling Technologies.
David C. Keezer
1993Let's Grade ALL the Faults.
Peter C. Maxwell
1993MCM Foundry Test Methodology and Implementation.
Lynn Roszel
1993Minimizing Test Time by Exploiting Parallelism in Macro Test.
Hans Bouwmeester, Steven Oostdijk, Frank Bouwman, Rudi Stans, Loek Thijssen, Frans P. M. Beenker
1993Mix Test: A Mixed-Signal Extension to a Digital Test System.
R. Mehtani, Bert Atzema, M. De Jonghe, Richard Morren, Geert Seuren, Taco Zwemstra
1993Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.
Yves Bertrand, Frédéric Bancel, Michel Renovell
1993Multiple Fault Diagnosis in Printed Circuit Boards.
S. J. Barnfield, Will R. Moore
1993Mutation-Based Testing of Concurrent Programs.
Richard H. Carver
1993Novel Test Pattern Generators for Pseudo-Exhaustive Testing.
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1993On Accurate Modeling and Efficient Simulation of CMOS Opens.
Chennian Di, Jochen A. G. Jess
1993On Selecting Flip-Flops for Partial Reset.
Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab
1993On the Design for Testability of Communication Software.
Samuel T. Chanson, Antonio Alfredo Ferreira Loureiro, Son T. Vuong
1993On the Evaluation of Software Inspections and Tests.
Jarir K. Chaar, Michael J. Halliday, Inderpal S. Bhandari, Ram Chillarege
1993PSBIST: A Partial-Scan Based Built-In Self-Test Scheme.
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
1993Parameter Monitoring: Advantages and Pitfalls.
M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess
1993Partial Scan Using Reverse Direction Empirical Testability.
Kee Sup Kim, Charles R. Kime
1993Partial Scan at the Register-Transfer Level.
Johannes Steensma, Francky Catthoor, Hugo De Man
1993Position Statement: ITC93 Boundary-Scan Panel.
Colin M. Maunder
1993Practical Application of Statistical Process Control in Semiconductor Manufacturing.
Brian Beck
1993Practical Considerations for Mixed-Signal Test Bus.
Nai-Chi Lee
1993Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993
1993Quality Testing Requires Quality Thinking.
Jerry M. Soden, Charles F. Hawkins
1993Quality and Single-Stuck Faults.
Edward J. McCluskey
1993Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.
Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone
1993Scan DFT: Why More Can Cost Less.
Prab Varma
1993Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -.
Udo Mahlstedt, Jürgen Alt
1993Software Regression Testing Success Story.
Michael A. Long
1993Structure and Metrology for an Analog Testability Bus.
Kenneth P. Parker, John E. McDermid, Stig Oresjo
1993Structured CBIST in ASICs.
Robert Gage
1993Switch-Level ATPG Using Constraint-Guided Line Justification.
Eun Sei Park, M. Ray Mercer
1993Synthesizing for Scan Dependence in Built-In Self-Testable Desings.
LaNae J. Avra, Edward J. McCluskey
1993System Level Interconnect Test in a Tristate Environment.
Frank W. Angelotti, Wayne A. Britson, Kerry T. Kaliszewski, Steve M. Douskey
1993Technology Independent Boundary Scan Synthesis (Technology and Physical Issues).
Markus Robinson, Frédéric Mailhot, Jim Konsevich
1993Terminating Transmission lines in the Test Environment.
Richard F. Herlein
1993Test Features of the HP PA7100LC Processor.
Don Douglas Josephson, Daniel J. Dixon, Barry J. Arnold
1993Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.
Eugeni Isern, Joan Figueras
1993Test Pattern Generation with Restrictors.
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
1993Test Synthesis from a User Perspective.
Gunnar Carlsson
1993Testability Features of the SuperSPARC
Rajiv Patel, Krishna Yarlagadda
1993Testable Programmable Digital Clock Pulse Control Elements.
Kenneth D. Wagner, Bernd Könemann
1993Testing Fully Testable Systems: A Case Study.
John W. Sheppard
1993The Cost of Quality: Reducing ASIC Defects with I
Rick Gayle
1993The Economics of Guardband Placement.
Richard H. Williams, Charles F. Hawkins
1993The Evolving Role of Testing in Open Systems Standards.
James F. Leathrum, K. A. Liburdy
1993The Impact of Commercial Off-The-Shelf (COTS) Equipment on System Test and Diagnosis.
William R. Simpson, John W. Sheppard
1993The Standard Mirror Boards (SMBs) Concept - An Innovative Improvement of Traditional ATE for up to 10 Mil Bare Board Testing.
Christophe Vaucher, Louis Balme
1993Timing Analyzer for Embedded Testing.
Arnold Frisch, Thomas Almy
1993Tools and Techniques for Converting Simulation Models into Test Patterns.
Tony Taylor
1993Towards a Test Standard for Board and System Level Mixed-Signal Interconnects.
Carl W. Thatcher, Rodham E. Tulloss
1993Using Boundary Scan Test to Test Random Access Memory Clusters.
Math Muris, Alex S. Biewenga
1993Utilizing Boundary Scan to Implement BIST.
Tom Langford
1993VINCI: Secure Test of a VLSI High-Speed Encryption System.
Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner
1993Very-Low-Voltage Testing for Weak CMOS Logic ICs.
Hong Hao, Edward J. McCluskey
1993Visualizing Test Information: A Novel Approach for Improving Testability.
Jan Moorman, Steven D. Millman
1993Workstation Based Parallel Test Generation.
Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan
1993i
J. S. Beasley, H. Ramamurthy, Jaime Ramírez-Angulo, Mark DeYong