ITC A

132 papers

YearTitle / Authors
1992A 3GHz, 144 Point Probe Fixture for Automatic IC Wafer Testing.
Daniel T. Hamling
1992A Boundary Scan Test Controller for Hierarchical BIST.
José M. M. Ferreira, Filipe S. Pinto, José Silva Matos
1992A Comparison of Defect Models for Fault Location with I
Robert C. Aitken
1992A Fast Testing Method for Sequential Circuits at the State Trasition Level.
Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee
1992A Framework for Boundary-Scan Based System Test Diagnosis.
Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau
1992A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination.
Sungju Park, Sheldon B. Akers
1992A Method of Jitter Measurement.
Eric Rosenfeld
1992A Mixed Signal Analog Test Bus Framework.
Richard Hulse
1992A Proposed Method of Accessing 1149.1 in a Backplane Environment.
Lee Whetsel
1992A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories.
Tom Chen, Glen Sunada
1992A Simulation Environment for Early Lifecycle Software Reliability Research and Prediction.
Anneliese von Mayrhauser, James Keables
1992A Small Test Generator for Large Designs.
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
1992A Steady-State Response Test Generation for Mixed-Signal Integrated Circuits.
Alaa F. Alani, Gerry Musgrave, Anthony P. Ambler
1992A Structure for Board-Level Mixed-Signal Testability.
Brian R. Wilkins
1992A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection.
Marcus Rimén, Joakim Ohlsson
1992A Suite of Novel Digital ATE Timing Calibration Methods.
Herbert Thaler, Lee Holt
1992A Test Generation Methodology for High-Performance Computer Chips and Modules.
Bernd Könemann, Phil Noto
1992A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1992A VXI Driver-Sensor Instrument with Large Tester Architecture.
Matthew L. Fichtenbaum, Robert J. Muller
1992AC Dynamic Testing of 20Bit Sigma-Delta Over-Sampling D/A Converter on a Mixed Signal Test System.
Masao Sugai, Takayuki Nakatani
1992AC Test Quality: Beyond Transition Fault Coverage.
Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen
1992ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits.
Pi-Yu Chung, Ibrahim N. Hajj
1992Advances in Membrane Probe Technology.
January Kister, Robert L. Franch
1992All Tests for a Fault Are Not Equally Valuable for Defect Detection.
Rohit Kapur, Jaehong Park, M. Ray Mercer
1992Amdahl Corporation Board Delay Test System.
Bejoy G. Oomman, Prasad Kongara, Chittaranjan Mallipeddi
1992An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan.
Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq
1992An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit Diagnostics.
Robert Trahan, Rex Kiang
1992An Architecture for a Reconfigurable IEEE 1149.n Master Controller Board.
Kevin T. Kornegay, Robert W. Brodersen
1992An Automated Optical On-Wager Probing System for Ultra-High-Speed ICs.
Mitsuru Shinagawa, Tadao Nagatsuma
1992An Evaluation of I
K. Sawada, S. Kayano
1992An Instruction Sequence Assembling Methodology for Testing Microprocessors.
Jaushin Lee, Janak H. Patel
1992An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays.
Pinaki Mazumder
1992An Open Modular Test Concept for the DSP KISS-16Vs.
Joachim Preißner, G.-H. Huaman-Bollo, Gisela Mahlich, Johannes Schuck, Hans Sahm, P. Weingart, Dirk Weinsziehr, J. Yeandel, R. Evans
1992Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs.
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
1992Applications of the IEEE P1149.5 Module Test and Maintenance Bus.
David L. Landis, Chuck Hudson, Patrick F. McHugh
1992Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults.
Matthew Melton, Franc Brglez
1992Automatic Test Program Generation for Mixed Signal ICs via Design to Test Link.
William Kao, Jean Xia, Tom Boydston
1992BIST Techniques for ASIC Design.
Gordon R. Mc Leod
1992Board Test DFT Model for Computer Products.
Mick Tegethoff, T. E. Figal, S. W. Hird
1992Boundary Scan Testing for Multichip Modules.
Stephen C. Hilla
1992Bridging Defects Resistance Measurements in a CMOS Process.
Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls
1992CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System.
Haruo Kato
1992CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults.
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
1992COM (Cost Oriented Memory) Testing.
T. Yamada, Akihiro Fujiwara, Michiko Inoue
1992Calibration Techniques for a Gigahertz Test System.
David C. Keezer, R. J. Wenzel
1992Can Concurrent Checkers Help BIST?
Sandeep K. Gupta, Dhiraj K. Pradhan
1992Circuit Design for Built-in Current Testing.
Yukiya Miura, Kozo Kinoshita
1992Correlation of Capacitive Load Delay.
Ran Edeleman, Ishai Kreiser
1992DRC-based Selection of Optimal Probing Points for Chip-Internal Measurements.
R. Scharf, Claus Kuntzsch, Klaus Helmreich, Werner Wolz, Klaus D. Müller-Glaser
1992Delay Test: The Next Frontier for LSSD Test Systems.
Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams
1992Design Verification of a High Density Computer Using IEEE 1149.1.
Wayne T. Daniel
1992Design for Test Approaches to Mixed-Signal Testing.
Madhuri Jarwala
1992Design for Testability Using Architectural Descriptions.
Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992Designing for Software Testability Using Automated Oracles.
James M. Bieman, Hwei Yin
1992Detection of "Undetectable" Faults Using I
Ravi K. Gulati, Weiwei Mao, Deepak K. Goel
1992Diagnostic Fault Simulation of Sequential Circuits.
Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel
1992Does Object-Oriented Programming Fit in the Real World of ATE?
Richard S. Levy
1992EDIF Test - The Upcoming Standard for Test Data Transfers.
Michael G. Wahl, Carol Pyron
1992Economic Impact of Type I Test Errors at System and Board Levels.
Christopher L. Henderson, Richard H. Williams, Charles F. Hawkins
1992Enhanced Probe Card Facilities At-Speed Wafer Probing in Very High Density Applications.
Eswar Subramanian, Randy Nelson
1992Functional Testing of Current Microprocessors (applied to the Intel i860
Ad J. van de Goor, Th. J. W. Verhallen
1992Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski
1992HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test.
Oliver F. Haberl, Thomas Kropf
1992High Performance Monolithic Verniers for VLSI Automatic Test Equipment.
R. Warren Necoechea
1992High Performance Pin Electronics with GaAs, A Contradiction in Terms?
Ulrich Schoettmer, Holger Engelhard
1992High Quality Testing of Embedded RAMs Using Circular Self-Test Path.
Andrzej Krasniewski, Slawomir Pilarski
1992High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation.
Jim Chapman
1992I
Roger Perry
1992IDA: A Tool for Computer-Aided Failure Analysis.
Alan C. Noble
1992IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic.
John Andrews
1992Impact of Boundary Scan Design on Delay Test.
E. Kofi Vida-Torku
1992Implementing 1149.1 on CMOS Microprocessors.
William C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns
1992Improving Total IC Design Quality Using Application Mode Testing.
R. Mehtani, M. De Jonghe, Richard Morren, Keith Baker
1992In-Process Inspection Technique for Active-Matrix LCD Panels.
Takashi Kido
1992Intelligent Fault Localization in Software.
Ilene Burnstein, Nitya Jani, Steve Mannina, Joe Tamsevicius, Michael Goldshteyn, Louis Lendi
1992Interconnect and Delay Testing with a 4800-Pin Board Tester.
Shuichi Kameyama, Hideyuki Ohara, Chihiro Endo, Naoki Takayama
1992Is Burn-In Burned-Out - Part 2.
Noel E. Donlin
1992Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study.
Barry Caldwell, Tom Langford
1992LSSD Compatible and Concurrently Testable Ram.
Hideshi Maeno, Koji Nii, S. Sakayanagi, S. Kato
1992MCM Test Using Available Technology.
David C. Keezer
1992Macro Testability: The Results of Production Device Applications.
Frank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, Frans P. M. Beenker
1992Memory Interconnection Test at Board Level.
Frans G. M. de Jong, Adriaan J. de Lind van Wijngaarden
1992Merging Concurrent Checking and Off-line BIST.
Xiaoling Sun, Micaela Serra
1992Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.
Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus
1992Non-Conventional Faults in BiCMOS Digital Circuits.
Siyad C. Ma, Edward J. McCluskey
1992On the Design of Self-Checking Boundary Scannable Boards.
Marcelo Lubaszewski, Bernard Courtois
1992One-Pass Redundancy Identification and Removal.
Miron Abramovici, Mahesh A. Iyer
1992Optimal Sequencing of Scan Registers.
Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
1992Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata.
Jos van Sas, Francky Catthoor, Hugo De Man
1992Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs.
Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
1992Parity-Scan Design to Reduce the Cost of Test Application.
Hideo Fujiwara, Akihiro Yamamoto
1992Physical DFT for High Coverage of Realistic Faults.
M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1992Position of Component Testing in Total Quality Management (TQM).
Babur Mustafa Pulat, Lauren M. Streb
1992Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992
1992Progress in DFT: A Personal View.
Ben Bennetts
1992Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
Wolfgang Kunz, Dhiraj K. Pradhan
1992Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.
Weiwei Mao, Michael D. Ciletti
1992ScanBIST: A Multi-frequency Scan-based BIST Method.
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
1992Self-Test Scheduling with Bounded Test Execution.
Albrecht P. Stroele
1992Sequential Circuit Diagnosis Based on Formal Verification Techniques.
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1992Sequential Redundancy Identification Using Verification Techniques.
John Moondanos, Jacob A. Abraham
1992Sequential Test Generation Based on Real-Value Logic.
Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
1992Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits.
Stephen C. Bateman, William H. Kao
1992Skewed-Load Transition Test: Part 1, Calculus.
Jacob Savir
1992Skewed-Load Transition Test: Part 2, Coverage.
Srinivas Patil, Jacob Savir
1992Software Testing: Opportunity and Nightmare.
Anneliese von Mayrhauser
1992Software Testing: Theory and Practice.
Simeon C. Ntafos
1992Successful Implementation of SPC in Semiconductor Final Test.
Sarkis Ourfalian
1992System Perspective on Diagnostic Testing.
William R. Simpson, John W. Sheppard
1992System Test: What is it? Why Bother Defining It?
Maury A. Smeyne
1992System Testing: The Future for All of Us.
Charles F. Hawkins
1992TGEN: Flexible Timing Generator Architecture.
Timothy Alton
1992Test Generation and Concurrent Error Detection in Current-Mode A/D Converters.
Shoba Krishnan, Sondes Sahli, Chin-Long Wey
1992Test/Agent: CAD-integrated Automatic Generation of Test Programs.
R. Arnold, Michael Chowanetz, Werner Wolz, Klaus D. Müller-Glaser
1992Testable Designs of Sequential Circuits Under Highly Observable Condition.
Xiaoqing Wen, Kozo Kinoshita
1992Testing Errors: Data and Calculations in an IC Manufacturing Process.
Richard H. Williams, R. Glenn Wagner, Charles F. Hawkins
1992Testing Video Processors.
Paul Kelley
1992Testing a DSP-Based Mixed-Signal Telecommunications Chip.
Paul Astrachan, Todd Brooks, Jody Everett, Wai-On Law, Kenneth McIntyre, Chuong Nguyen, Charles Weng
1992The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADC.
Akinori Maeda
1992The Effectiveness of I
Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang
1992The Great ATE Robbery.
Andrew Rappaport
1992The Production Implementation of a Linear Error Modeling Technique.
Timothy Daniel Lyons
1992The Reality of Object Oriented Solutions for ATE.
James R. Ward
1992Time-to-Market: An Issue in Mixed-signal vs. Analogue.
Keith Baker
1992Timing-Per-Pin Flexibility at Shared-Resource Cost.
Gary Fehr
1992Transistor Fault Coverage for Self-Testing CMOS Checkers.
Peter Lidén, Peter Dahlgren, Jan Torin
1992Transition Fault Simulation for Sequential Circuits.
Kwang-Ting Cheng
1992Transparent BIST for RAMs.
Michael Nicolaidis
1992Using EDIF for Transfer of Test Data: Practical Experience.
Bas Verhelst, Richard Morren, Keith Baker
1992Using Tester Repeatability to Improve Yields.
Robert James Montoya
1992VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test Vectors.
Gaspare Pantano, Dave Rolince
1992Warning: 100% Fault Coverage May Be Misleading!!
Miron Abramovici, Prashant S. Parikh