| 1990 | A BIST scheme using microprogram ROM for large capacity memories. Hiroki Koike, Toshio Takeshima, Masahide Takada |
| 1990 | A comprehensive approach for modeling and testing analog and mixed-signal devices. T. Michael Souders, Gerard N. Stenbakken |
| 1990 | A design-for-test methodology for active analog filters. Mani Soma |
| 1990 | A diagnostic test pattern generation algorithm. Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda |
| 1990 | A fine pitch probe technology for VLSI wafer testing. T. Tada, R. Takagi, S. Nakao, M. Hyozo, T. Arakawa, K. Sawada, M. Ueda |
| 1990 | A fourth generation analog incircuit program generator. David T. Crook |
| 1990 | A high-speed pin-memory architecture using multiport dynamic RAMs. Sheng-Jen Tsai, Wha-Joon Lee |
| 1990 | A language for describing boundary-scan devices. Kenneth P. Parker, Stig Oresjo |
| 1990 | A method to calculate necessary assignments in algorithmic test pattern generation. Janusz Rajski, Henry Cox |
| 1990 | A multiple seed linear feedback shift register. Jacob Savir, William H. McAnney |
| 1990 | A new approach to mixed-signal diagnosis. Ravi Rastogi, Kenneth F. Sierzega |
| 1990 | A new procedure for weighted random built-in self-test. Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie |
| 1990 | A novel built-in self-repair approach to VLSI memory yield enhancement. Pinaki Mazumder, Jih-Shyr Yih |
| 1990 | A picosecond external electro-optic prober using laser diodes. Mitsuru Shinagawa, Tadao Nagatsuma |
| 1990 | A rapid dither algorithm advances A/D converter testing. Jack Weimer, Kevin Baade, John Fitzsimmons, Brian Lowe |
| 1990 | A study of faulty signatures using a matrix formulation. John C. Chan, Jacob A. Abraham |
| 1990 | A study of the optimization of DC parametric tests. J. Morris Chang |
| 1990 | A testable design of logic circuits under highly observable condition. Xiaoqing Wen, Kozo Kinoshita |
| 1990 | AC product defect level and yield loss. Jacob Savir |
| 1990 | ASIC CAD system based on hierarchical design-for-testability. Michiaki Emori, Takashi Aikyo, Yasuhide Machida, Jun-ichi Shikatani |
| 1990 | ASSIST (Allied Signal's Standardized Integrated Scan Test). Gordon Sapp |
| 1990 | ATE-based functional ISDN testing. Kenneth Lanier |
| 1990 | ATPG for ultra-large structured designs. John A. Waicukauski, Paul A. Shupe, David Giramma, Arshad Matin |
| 1990 | ATPG issues for board designs implementing boundary scan. Don Sterba, Andy Halliday, Don McClean |
| 1990 | An advanced test system architecture for synchronous and asynchronous control of mixed signal device testing. Jun Kurita, Nobuyuki Kasuga, Kiyoyasu Hiwada |
| 1990 | An analysis of ATE computational architecture. Anthony Taylor |
| 1990 | An architecture for high-speed analog in-circuit testing. Larry Klein, John Bridgeman |
| 1990 | An empirical relationship between test transparency and fault coverage. Robert B. Elo |
| 1990 | An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal |
| 1990 | An improved procedure to test CMOS ICs for latch-up. Roberto Menozzi, Massimo Lanzoni, Luca Selmi, Bruno Riccò |
| 1990 | An interactive environment for the transparent logic simulation and testing of integrated circuits. Grant L. Castrodale, Apostolos Dollas, William T. Krakow |
| 1990 | An optimization based approach to the partial scan design problem. Vivek Chickermane, Janak H. Patel |
| 1990 | Analog test requirements of linear echo cancellation ISDN devices. David K. Oka |
| 1990 | Analysis of cellular automata used as pseudorandom pattern generators. Paul H. Bardell |
| 1990 | Analysis of failures on memories using expert system techniques. Thierry Viacroze, Marc Lequeux |
| 1990 | Arrangement of latches in scan-path design to improve delay fault coverage. Weiwei Mao, Michael D. Ciletti |
| 1990 | Automatic electro-optical testing of automobile dashboard displays in a factory environment. Frank J. Langley, C. A. Robinson, R. A. Passero |
| 1990 | Boundary scan test used at board level: moving towards reality. Frans G. M. de Jong |
| 1990 | Bridging faults and their implication to PLAs. V. Chandramouli, Ravi K. Gulati, Ramaswami Dandapani, Deepak K. Goel |
| 1990 | Built-in self-test in a 24 bit floating point digital signal processor. Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda |
| 1990 | CMOS bridging fault detection. Thomas M. Storey, Wojciech Maly |
| 1990 | CMP3F: a high speed fault simulator for the Connection Machine. Ajit Agrawal, Debashis Bhattacharya |
| 1990 | Cellular automata based self-test for programmable data paths. Jos van Sas, Francky Catthoor, Hugo De Man |
| 1990 | Challenge of design and test of ultra-large-scale circuits. Akihiko Yamada |
| 1990 | Color reproduction test for CCD image sensors. Haruo Kato |
| 1990 | Complete self-test architecture for a coprocessor [cryptography]. Thomas M. Schwair, Hartmut C. Ritter |
| 1990 | Computer-aided design of pseudoexhaustive BIST for semiregular circuits. Chau-Chin Su, Charles R. Kime |
| 1990 | Concurrent engineering. Al Lowenstein, Steve Schlosser, Greg Winter |
| 1990 | Criteria for analyzing high frequency testing performance of VLSI automatic test equipment. Phil Burlison |
| 1990 | Critical parameters for high-performance dynamic response measurements. Donald F. Murray, C. Michael Nash |
| 1990 | Current testing. Wojciech Maly |
| 1990 | Design of integrated circuits fully testable for delay-faults and multifaults. Srinivas Devadas, Kurt Keutzer |
| 1990 | Design of scan-testable CMOS sequential circuits. Bong-Hee Park, Premachandran R. Menon |
| 1990 | Design of signature circuits based on weight distributions of error-correcting codes. Kazuhiko Iwasaki, Noboru Yamaguchi |
| 1990 | Development of a new standard for test. William W. Sebesta, Bas Verhelst, Michael G. Wahl |
| 1990 | Diagnosing CMOS bridging faults with stuck-at fault dictionaries. Steven D. Millman, Edward J. McCluskey, John M. Acken |
| 1990 | Diagnosis for wiring interconnects. Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu |
| 1990 | Direct access test scheme-design of block and core cells for embedded ASICs. Venkata R. Immaneni, Srinivas Raman |
| 1990 | EEODM: An effective BIST scheme for ROMs. Yervant Zorian, André Ivanov |
| 1990 | Efficient UBIST implementation for microprocessor sequencing parts. Michael Nicolaidis |
| 1990 | Empirical failure analysis and validation of fault models in CMOS VLSI. Ashish Pancholy, Janusz Rajski, Larry J. McNaughton |
| 1990 | Error masking in self-testable circuits. Albrecht P. Stroele, Hans-Joachim Wunderlich |
| 1990 | Errors in testing. Richard H. Williams, Charles F. Hawkins |
| 1990 | Event qualification: a gateway to at-speed system testing. Lee Whetsel |
| 1990 | Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases. William H. Nicholls, Arnold W. Nordsieck, Mani Soma |
| 1990 | Extending binary searches to two and three dimensions [IC testing]. Robert L. Hickling |
| 1990 | Failure coverage of functional test methods: a comparative experimental evaluation. Raoul Velazco, Catherine Bellon, Bernard Martinet |
| 1990 | Failure probability algorithm for test systems to reduce false alarms. Don R. Allen |
| 1990 | Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniques. Billy W. Sprinkle |
| 1990 | Fast embedded A/D converter testing using the microcontroller's resources. Ram Bobba, B. Stevens |
| 1990 | Fault grading the Intel 80486. Naga Gollakota, Ahmad Zaidi |
| 1990 | Fault simulation of logic designs on parallel processors with distributed memory. Leendert M. Huisman, Raja Daoud |
| 1990 | Frequency enhancement of digital VLSI test systems. Leslie Ackner, Mark R. Barber |
| 1990 | From specification to measurement: the bottleneck in analog industrial testing. Robert Van Rijsinge, A. A. R. M. Haggenburg, C. de Vries, Hans Wallinga |
| 1990 | Functional and I R. Meershoek, Bas Verhelst, Rory McInerney, Loek Thijssen |
| 1990 | Functional test and diagnosis: a proposed JTAG sample mode scan tester. Mark F. Lefebvre |
| 1990 | Functional test generation for finite state machines. Kwang-Ting Cheng, Jing-Yang Jou |
| 1990 | Generating pseudo-exhaustive vectors for external testing. Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl |
| 1990 | Global cost functions for test generation. Miron Abramovici, David T. Miller, R. Henning |
| 1990 | Hierarchical self-test concept based on the JTAG standard. Johann Maierhofer |
| 1990 | Hierarchical test assembly for macro based VLSI design. Jens Leenstra, Lambert Spaanenburg |
| 1990 | High-speed fixture interconnects for mixed-signal IC testing. Joseph A. Mielke, Keith A. Pope |
| 1990 | I Keith Baker, Bas Verhelst |
| 1990 | Identification of faulty processing elements by space-time compression of test responses. Mark G. Karpovsky, Lev B. Levitin, Feodor S. Vainstein |
| 1990 | Improving wafer sort yields with radius-tip probes. Samuel Schleifer |
| 1990 | Increased CMOS IC stuck-at fault coverage with reduced I Ronald R. Fritzemeier, Jerry M. Soden, R. Keith Treece, Charles F. Hawkins |
| 1990 | Innovative techniques for improved testability. Endre F. Sarkany, Robert F. Lusch |
| 1990 | Integrating boundary scan test into an ASIC design flow. Math Muris |
| 1990 | Interconnect testing of boards with partial boundary scan. Gordon D. Robinson, John G. Deshayes |
| 1990 | Jitter minimization technique for mixed signal testing. Yasuo Furukawa, Makoto Kimura, Masao Sugai, Shinichi Kimura, Michael Purtell |
| 1990 | Macro-testability and the VSP. R. Mehtani, Keith Baker, C. M. Huizer, P. J. Hynes, Jos van Beers |
| 1990 | Marginal fault diagnosis based on e-beam static fault imaging with CAD interface. Norio Kuji, Kiyoshi Matsumoto |
| 1990 | Minimal overhead modification of iterative logic arrays for C-testability. Tsu-Wei Ku, Mani Soma |
| 1990 | Mixed-mode ATPG under input constraints. C. Thomas Glover |
| 1990 | Multiple path sensitization for hierarchical circuit testing. Chau-Chin Su, Charles R. Kime |
| 1990 | Multiplexing test system channels for data rates above 1 Gb/s. David C. Keezer |
| 1990 | Networking verification process and environments: an extension of the product realization process for new network capabilities. Y. M. Mastoris, P. D. Nash |
| 1990 | New approach to integrate LSI design databases with e-beam tester. Arthur Hu, Hironobu Niijima |
| 1990 | Obstacles and an approach towards concurrent engineering. Melvin A. Breuer |
| 1990 | On automatic testpoint insertion in sequential circuits. Harald Gundlach, Klaus D. Müller-Glaser |
| 1990 | On the charge sharing problem in CMOS stuck-open fault testing. Kuen-Jong Lee, Melvin A. Breuer |
| 1990 | On the evaluation of process-fault tolerance ability of CMOS integrated circuits. Etienne Sicard, Kozo Kinoshita |
| 1990 | Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration. David L. Landis, Padmaraj Singh |
| 1990 | Optimized testing of meshes. Miroslaw Malek, Banu Özden |
| 1990 | Parallel pattern fault simulation based on stem faults in combinational circuits. Ohyoung Song, Premachandran R. Menon |
| 1990 | Practical partitioning for testability with time-shared boundary scan. Rafic Z. Makki, Krisbnm Palaniswami |
| 1990 | Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990 |
| 1990 | QML (qualified manufacturing line): a method of providing high quality integrated circuits. Noel E. Donlin |
| 1990 | Realization of an efficient design verification test used on a microinstruction controlled self test. Yasuyuki Nozuyama |
| 1990 | Scan based guided probe technology delivers Cyclone to the market. Chul J. Choi |
| 1990 | Scan test architectures for digital board testers. Matthew L. Fichtenbaum, Gordon D. Robinson |
| 1990 | Sequencer Per Pin test system architecture. Burnell West, Tom Napier |
| 1990 | Sequential logic synthesis for testability using register-transfer level descriptions. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | Single-fault fault collapsing analysis in sequential logic circuits. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen |
| 1990 | State transition graph analysis as a key to BIST fault coverage. Ove Brynestad, Einar J. Aas, Anne E. Vallestad |
| 1990 | Stress profile derivation-an empirical approach. Alan C. Walker |
| 1990 | TDRC-a symbolic simulation based design for testability rules checker. Prab Varma |
| 1990 | Technique for transfer of analog prototypes (DV's) to production. Michael P. Palumbo |
| 1990 | Test engineers role in QML. Robert W. Thomas |
| 1990 | Test features of the MC145472 ISDN U-transceivers. Luis A. Bonet, J. Ganger, Jim Girardeau, Carlos Greaves, M. Pendleton, David Yatim |
| 1990 | Testability considerations in the design of the MC68340 Integrated Processor Unit. Philip E. Bishop, Grady Giles, Sudarshan Iyengar, C. Thomas Glover, Wai-On Law |
| 1990 | Testability features of the 68040. Michael G. Gallup, William Ledbetter Jr., Ralph McGarity, Steve McMahan, Kenneth Scheuer, Clark G. Shepard, Lal Sood |
| 1990 | Testability implemented in the VAX 6000 model 400. John Sweeney |
| 1990 | Testability preserving transformations in multi-level logic synthesis. Janusz Rajski, Jagadeesh Vasudevamurthy |
| 1990 | Testable design and support tool for cell based test. Takuji Ogihara, Yasushi Koseko, Genichi Yonemori, Hiroyuki Kawai |
| 1990 | Testing for parametric faults in static CMOS circuits. F. Joel Ferguson, Martin Taylor, Tracy Larrabee |
| 1990 | The Waveform and Vector Exchange Specification (WAVES). Larry Moran, Robert Hillman, Phil Burlison, Tom Gurda |
| 1990 | The boundary-scan master: target applications and functional requirements. Chi W. Yau, Najmi T. Jarwala |
| 1990 | The capability of capability indices with an application to guardbanding in a test environment. Paul Mullenix |
| 1990 | The dynamic reduction of fault simulation. Fadi Maamari, Janusz Rajski |
| 1990 | The use of tolerance intervals in the characterization of semiconductor devices. Yolanda T. Hadeed, Kevin T. Lewis |
| 1990 | Time margin issues in disk drive testing. Durwin Gill |
| 1990 | Towards a standard approach for controlling board-level test functions. Bulent I. Dervisoglu |
| 1990 | Wave+: An easy-to-use vector generation language for compilers. Masahiro Handa, Russel L. Steinweg |
| 1990 | Weighted random test program generation for a per-pin tester. Jeff Gartner, B. Driscoll, Donato O. Forlenza, Orazio P. Forlenza, Timothy J. Koprowski, T. Lizambri, R. Olsen, S. Robertson, P. Ryan, A. Walter |
| 1990 | Why is less information from logic simulation more useful in fault simulation? Sheldon B. Akers Jr., Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan |
| 1990 | Why, I Steven D. McEuen |
| 1990 | Zero defects or zero stuck-at faults-CMOS IC process improvement with I Jerry M. Soden, Ronald R. Fritzemeier, Charles F. Hawkins |
| 1990 | enVision: the inside story. Don Organ |