ITC A

136 papers

YearTitle / Authors
1988: A Parallel Algorithm for Fault Simulation on the Connection Machine.
Vinod Narayanan, Vijay Pitchumani
1988: Test Scheduling for High Performance VLSI System Implementations.
John Y. Sayah, Charles R. Kime
1988A BIST Design of Structured Arrays with Fault-Tolerant Layout.
Mehdi Katoozi, Mani Soma
1988A High Level Approach to Integrating Design and Test.
John Ivie
1988A High-Resolution Waveform Analysis Tool.
Patrick M. Powers
1988A Knowledge Representation Scheme for DFT.
Desmond F. D'Souza
1988A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator.
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
1988A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability.
Sandeep K. Gupta, Dhiraj K. Pradhan
1988A Realistic Self-Test Machine for Static Random Access Memories.
Frans P. M. Beenker, Rob Dekker, Loek Thijssen
1988A Strategy for Generating Functional Tests from Device Simulations.
Cristopher Merritt
1988A Test and Maintenance Controller for a Module Containing Testable Chips.
Melvin A. Breuer, Jung-Cheun Lien
1988An Advanced Data Compaction Approach for Test During Burn-In.
Birger Schneider, Peter Oestergaard
1988An Algorithmic Branch and Bound Method for PLA Test Pattern Generation.
Markus Robinson, Janusz Rajski
1988An Expert Test Program Generation System for Per-Pin Testers.
A. Walter, Y. Kleinman, L. Edelshteyn, Jeff Gartner
1988An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli
1988An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory.
Pinaki Mazumder
1988Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits.
Catherine Bellon, Raoul Velazco, Haissam Ziade
1988Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging.
Steve Grennan
1988Automatic Location of IC Design Errors Using Beam System.
M. Melgara, M. Battu, P. Garino, J. Dowe, Y. J. Vernay, M. Marzouki, Francis M. Boland
1988Board-Level Diagnosis by Signature Analysis.
Mark G. Karpovsky, Prawat Nagvajara
1988Boundary Scan with Cellular-Based Built-In Self-Test.
Clay Gloster, Franc Brglez
1988Boundary Scan: The ATE Vendors' View.
Phil Collins
1988Built-In Test Compiler in an ASIC Environment.
Eric Archambeau, Ken Van Egmond
1988Built-In Test Strategy for Next Generation Military Avionic Hardware.
Donald H. Merliho, John Hadjilogiou
1988CAD Tools for Supporting System Design for Testability.
Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson
1988CIM , Electronics Manufacturing and ATE.
Neil Hutchinson
1988Characteristic Impedance and Coupling Coefficients for Multilayer PC Boards.
J. R. Birchak, H. K. Haill
1988Circular BIST with Partial Scan.
M. M. Pradhan, E. J. O'Brien, S. L. Lam, James Beausang
1988Concurrent Control of Multiple BIT Structures.
Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
1988Concurrent Off-Phase Built-in Self-Test of Dormant Logic.
Leon J. Sigal, Charles R. Kime
1988Contactors for Testing at High Frequencies.
Bernd Reichelmann
1988Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors.
Kent D. Wilken, John Paul Shen
1988DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests.
M. J. Marlett, Jacob A. Abraham
1988D^3FS: A Demand Driven Deductive Fault Simulator.
Steven P. Smith, Bill Underwood, M. Ray Mercer
1988Defining a Standard for Fault Simulator Evaluation.
Sami A. Al-Arian, Kevin A. Kwiat
1988Delay Test Generation 1: Concepts and Coverage Metrics.
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
1988Delay Test Generation 2: Algebra and Algorithms.
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
1988Design for Test and the Cost of Quality.
Chris Salzmann, Martin Funcell, Richard Taylor
1988Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology.
Matthias Gruetzner
1988Design for Testability of Mixed Signal Integrated Circuits.
Kenneth D. Wagner, Thomas W. Williams
1988Design for Testability of a 32-Bit Microprocessor, the TX1.
Yasuyuki Nozuyama, Akira Nishimura, Jun Iwamura
1988Designing State Machines for Testability.
Michael Treseler
1988Designs for Diagnosability and Reliability in VLSI Systems.
Stephen Y. H. Su, Hede Ma
1988Detecting Bridging Faults with Stuck-at Test Sets.
Steven D. Millman, Edward J. McCluskey
1988Detection of Control Flow Errors Using Signature and Checking Instructions.
Janusz Sosnowski
1988Detection of Hard Faults in a Combinational Circuit Using Budget Constraints.
David Stannard, Bozena Kaminska
1988Determination of Safe Back-Driving Currents in Bond Wires and Dice.
G. J. Hill, B. C. Roberts, C. P. Strudwick
1988Digital Testing, Theory and Practice.
Samiha Mourad
1988Do the Designs Work ?
Kenneth Rose
1988Dual Port Static RAM Testing.
Manuel J. Raposa
1988Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays.
Michael Demjanenko, Shambhu J. Upadhyaya
1988Electron Beam Tester Integrated into a VLSI Tester.
Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum
1988Elimination of Incoming Test Based Upon In-Process Failure and Repair Costs.
W. David Ballew, Lauren M. Streb
1988Emulative Testing at the Bus Speed Limit.
Douglas B. Arnett, K. S. Bhaskar
1988Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique.
Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone
1988Error Detection with Latency in Sequential Circuits.
Lawrence P. Holmquist, Larry L. Kinney
1988Evaluating the Limitations of High-Speed Board Testers.
John Arena
1988Evaluation of System BIST Using Computational Performance Measures.
David L. Landis, Daniel C. Muha
1988Experiences with Concurrent Fault Simulation of Diagnostic Programs.
Stephen R. Demba, Ernst G. Ulrich, Karen Panetta, David Giramma
1988Expert System for the Functional Test Program Generation of Digital Electronic Circuit Boards.
Stephen M. Lea, Nigel Brown, Tim Katz, Phil Collins
1988Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis.
John Paul Shen, F. Joel Ferguson
1988Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation.
William H. Nicholls, Mani Soma
1988Fault Detection Effectiveness of Weighted Random Patterns.
John A. Waicukauski, Eric Lindbloom
1988Fault Detection of Combinational Circuits Based on Supply Current.
Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami
1988Fault Isolation in Grey Systems.
Stephen Y. H. Su, Hede Ma
1988Fault Modeling and Test Algorithm Development.
Frans P. M. Beenker, Rob Dekker, Loek Thijssen
1988Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level.
Jean Paul Caisso, Bernard Courtois
1988Flexible Deep Memory Architecture Aids Program Development.
John L. Russo
1988Functional Test Program Generation Through interactive Graphics.
Cihan Tinaztepe, Bülent Özgüç
1988G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing.
Gabriel M. Silberman, Ilan Y. Spillinger
1988GaAs Driver and Sensor for a High-Speed Test System.
Sheng-Jen Tsai, Charles D. Hechtman
1988Hierarchical Test Generation Using Precomputed Tests for Modules.
Brian T. Murray, John P. Hayes
1988High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test System.
Dean J. Kratzer, Steve Barton, Francois J. Henley, David A. Plomgrem
1988IC Quality and Test Transparency.
Edward J. McCluskey, Fred Buelow
1988Identification of Failing Tests with Cycling Registers.
Jacob Savir, William H. McAnney
1988Impact of Testability Standards on University Research and Instruction.
Charles R. Kime
1988In-Circuit Test Fixture.
Charles D. Hechtman
1988Integrated Pin Electronics for a VLSI Test System.
Christopher W. Branson, Don Murray, Steve Sullivan
1988Integrated Test Logic for Video ICs.
John Beck, James Pappas, Robert Rose, Larry Seiler
1988Key Technologies for 500 MHz VLSI Test System "ULTIMATE".
Teruo Tamama, Naoaki Narumi, Tai-ichi Otsuji, Masao Suzuki, Tsuneta Sudo
1988Managing Quality : Today's Opportunities, Tomorrow's Challenges.
A. Blanton Godfrey
1988Managing the ASIC Design to Test Process.
Gary D. Culbertson
1988Membrane Probe Card Technology (the Future for High Performance Wafer Test).
Brian Leslie, Farid Matta
1988Microprocessor Testing by Instruction Sequences Derived from Random Patterns.
Hans Peter Klug
1988Multiple Distributions for Biased Random Test Patterns.
Hans-Joachim Wunderlich
1988New Automated Prober Support for High Pincount Test Heads.
T. Roland Fredriksen, David Grano
1988New Testing Equipment for SMT PC Boards.
Luis Balme, Anne Mignotte, Jean-Yves Monari, Patrick Pondaven, Christophe Vaucher
1988On Behavior Fault Modeling for Combinational Digital Designs.
Tapan J. Chakraborty, Sumit Ghosh
1988On Benchmarking Digital Testing Systems.
Samiha Mourad, Edward J. McCluskey
1988On Multiple Fault Coverage and Aliasing Probability Measures.
Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
1988On the Detection of Delay Faults.
Ankan K. Pramanick, Sudhakar M. Reddy
1988On the Testing of Multiplexers.
Samy Makar, Edward J. McCluskey
1988Optical Testing of Printed Circuit Boards.
G. Tremblay, P. Meyrueix, J. C. Peuzin
1988Optimal Logic Synthesis and Testability : Two Sides of the Same Coin.
Alberto L. Sangiovanni-Vincentelli
1988Optimal Scheduling of Signature Analysis for VLSI Testing.
C. Mani Krishna, Yann-Hang Lee
1988Optimal Use of Timing Resources: A Crucial Step in Test Program Generation.
Ji-en Morris Chang, William T. Krakow
1988PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices.
Yuichi Kawabata, Masami Maruyama, Al Tejeda
1988Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE".
Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo
1988Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation.
Jon G. Udeli Jr., Edward J. McCluskey
1988Practical Production Testing of ISDN Circuit Boards.
Robert E. McAuliffe
1988Practice and Theory.
Edward J. McCluskey
1988Predicting and Obtaining High Final Test Yields.
Raymond J. Balzer, Greg A. Larsen
1988Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988
1988RTRAM: Reconfigurable and Testable Multi-Bit RAM Design.
Dhiraj K. Pradhan, Nirmala R. Kamath
1988Reconfigurable Hardware for Pseudo-Exhaustive Test.
Jon G. Udeli Jr.
1988Reliability Testing by Precise Electrical Measurement.
A. P. Dorey, B. K. Jones, Andrew Mark David Richardson, P. C. Russell, Y. Z. Xu
1988Robust Tests for Parity Trees.
Sandip Kundu, Sudhakar M. Reddy
1988Scan Diagnostic Strategy for the Series 10000 Prism Workstation.
Mike Ricchetti, John Hoglund
1988Scan Path and Beyond : The Road to Improved ASIC Testability.
Lutz P. Henckels
1988Semiconductor Perspective on Test Standards.
Pete Fleming
1988Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL).
Kenneth R. Stuchlik
1988Software Environment for 500 MHz VLSI Test System "ULTIMATE".
Tohru Adachi, M. Tanno, Tsuneta Sudo
1988Some New Techniques in Waveshape Capture and Analysis.
Arthur E. Downey, Kazuhiko Matsuda
1988Standardization of ATE Timing Accuracy Specifications.
Marc Mydill
1988Statistical Delay Fault Coverage and Defect Level for Delay Faults.
Eun Sei Park, Thomas W. Williams, M. Ray Mercer
1988Stuck-Open and Transition Fault Testing in CMOS Complex Gates.
Henry Cox, Janusz Rajski
1988Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism.
Deborah Machlin, David Gross, Sudhir Kadkade, Ernst G. Ulrich
1988Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.
Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988System Level Fault Dictionary Generation.
Hidetoshi Tanaka, Masato Kawai, Izumi Sugasaki, Tadanobu Hakuba
1988TASTE: A Tool for Analog System Testability Evaluation.
Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff
1988Techniques for User Testing of the 68882.
Mark Marshall
1988Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System.
Francois J. Henley, Hee-June Choi
1988Testability Features in the TMS370 Family of Microcomputers.
Theo J. Powell, Fred Hwang, Bill Johnson
1988Testability Features of a 32 Kbps ADPCM Transcoder.
Luis A. Bonet
1988Testability Using Random Access Test Register.
Cuong Bui
1988Testing and Diagnosis of Interconnects Using Boundary Scan Architecture.
Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski
1988The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions.
Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko
1988The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource.
Peter N. Marinos
1988Threading of Multiple Scan Paths in a VLSI Circuit.
S. Bhawmick, M. S. Khaira, P. P. Mishra, A. Das, A. Dasgupta, P. Palchaudhury
1988Timing Generation for DSP Testing.
Eric Rosenfeld
1988Trouble-Shooting: A Key to Process Improvement.
Chi W. Yau, Song-Lin Chang, Bruce F. Jordan, Joe J. Schwermann, Joan A. Wellman
1988Using Scan Technology for Debug and Diagnostics in a Workstation Environment.
Bulent I. Dervisoglu
1988Value of Testability Standards in Testing Commercial Products.
David J. Richards
1988Very High Density Probing.
C. Barsotti, S. Tremaine, M. Bonham
1988WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test.
Fardad Siavoshi
1988What is the Path to Fast Fault Simulation?
Miron Abramovici, Balaji Krishnamurthy, Rob Mathews, Bill Rogers, Michael Schulz, Sharad Seth, John A. Waicukauski