ISPASS B

31 papers

YearTitle / Authors
2005A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.
Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu
2005A Trace-Driven Simulator For Palm OS Devices.
Hyrum Carroll, J. Kelly Flanagan, Satish Baniya
2005Accelerating Multiprocessor Simulation with a Memory Timestamp Record.
Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovic
2005Analysis of Network Processing Workloads.
Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
2005Anatomy and Performance of SSL Processing.
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan
2005Architectural Characterization of Processor Affinity in Network Processing.
Annie P. Foong, Jason Fung, Donald Newell, Seth Abraham, Peggy Irelan, Alex Lopez-Estrada
2005Balancing Performance and Reliability in the Memory Hierarchy.
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
2005BioBench: A Benchmark Suite of Bioinformatics Applications.
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung
2005Dataflow: A Complement to Superscalar.
Mihai Budiu, Pedro V. Artigas, Seth Copen Goldstein
2005EEMBC and the Purposes of Embedded Processor Benchmarking.
Markus Levy
2005Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison.
Magnus Ekman, Per Stenström
2005Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection.
Ram Srinivasan, Jeanine E. Cook, Shaun Cooper
2005IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings
2005Insight, not (random) numbers.
Thomas M. Conte
2005Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification.
Jeff Ringenberg, Chris Pelosi, David W. Oehmke, Trevor N. Mudge
2005Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites.
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, Lizy Kurian John
2005Motivation for Variable Length Intervals and Hierarchical Phase Behavior.
Jeremy Lau, Erez Perelman, Greg Hamerly, Timothy Sherwood, Brad Calder
2005On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.
Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero
2005On the provision of prioritization and soft qos in dynamically reconfigurable shared data-centers over infiniband.
Pavan Balaji, Sundeep Narravula, Karthikeyan Vaidyanathan, Hyun-Wook Jin, Dhabaleswar K. Panda
2005Panel Discussion: Architectures for the Future.
Erik R. Altman
2005Partitioning Multi-Threaded Processors with a Large Number of Threads.
Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas
2005Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering.
Raimir Holanda, Javier Verdú, Jorge García-Vidal, Mateo Valero
2005Performance Characterization of Java Applications on SMT Processors.
Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
2005Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors.
Jian Li, José F. Martínez
2005PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis.
Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
2005Pro-active Page Replacement for Scientific Applications: A Characterization.
Murali Vilayannur, Anand Sivasubramaniam, Mahmut T. Kandemir
2005Reaping the Benefit of Temporal Silence to Improve Communication Performance.
Kevin M. Lepak, Mikko H. Lipasti
2005Scalarization on Short Vector Machines.
Yuan Zhao, Ken Kennedy
2005Simulation Differences Between Academia and Industry: A Branch Prediction Case Study.
Gabriel H. Loh
2005Studying Thermal Management for Graphics-Processor Architectures.
Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
2005The Strong correlation Between Code Signatures and Performance.
Jeremy Lau, Jack Sampson, Erez Perelman, Greg Hamerly, Brad Calder