ISLPED A

65 papers

YearTitle / Authors
19980.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology.
Volker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau
19983D CMOS SOL for high performance computing.
Selim J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois
1998A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances.
Tamara I. Ahrens, Thomas H. Lee
1998A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology.
Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost
1998A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi
1998A high speed and low power SOL inverter using active body-bias.
Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin
1998A low power SRAM using auto-backgate-controlled MT-CMOS.
Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
1998A low power video processor.
Uzi Zangi, Ran Ginosar
1998A power optimization method considering glitch reduction by gate sizing.
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998A reconfigurable dual output low power digital PWM power converter.
Abram P. Dancy, Anantha P. Chandrakasan
1998A three-port adiabatic register file suitable for embedded applications.
Stephan Avery, Marwan A. Jabri
1998A unified approach in the analysis of latches and flip-flops for low-power systems.
Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
1998An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.
Catherine H. Gebotys, Robert J. Gebotys
1998Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos
1998Automatic characterization and modeling of power consumption in static RAMs.
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
1998CMOS VCOs for frequency synthesis in wireless biotelemetry.
Rafael J. Betancourt-Zamora, Thomas H. Lee
1998CMOS front end components for micropower RF wireless systems.
Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser
1998Decorrelating (DECOR) transformations for low-power adaptive filters.
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1998Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.
L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy
1998Emerging power management tools for processor design.
David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
1998Estimation of maximum power supply noise for deep sub-micron designs.
Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
1998Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
1998Fast high-level power estimation for control-flow intensive design.
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1998High performance DSPs - what's hot and what's not?
Bryan D. Ackland, Chris J. Nicol
1998Improving sampling efficiency for system level power estimation.
Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
1998Integrated DC/DC converter with digital controller.
Ferdinand Sluijs, Kees Hart, Wouter Groeneveld, Stephan Haag
1998Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.
Ki-Seok Chung, C. L. Liu
1998Low power and low voltage CMOS digital circuit techniques.
Christer Svensson, Atila Alvandpour
1998Low power architecture of the soft-output Viterbi algorithm.
David Garrett, Mircea R. Stan
1998Low power logic synthesis under a general delay model.
Unni Narayanan, Peichen Pan, C. L. Liu
1998Low power methodology and design techniques for processor design.
J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone
1998Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture.
Eric Y. Chou, A. J. Budrys, Kit M. Cham
1998Low threshold CMOS circuits with low standby current.
Mircea R. Stan
1998Low-energy embedded FPGA structures.
Eric Kusse, Jan M. Rabaey
1998Low-power embedded SRAM macros with current-mode read/write operations.
Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng
1998Low-power miniaturized information display systems.
Michael Bolotski, Phillip Alvelda
1998Low-swing interconnect interface circuits.
Hui Zhang, Jan M. Rabaey
1998Memory modeling for system synthesis.
Sari L. Coumeri, Donald E. Thomas
1998Minimum supply voltage for bulk Si CMOS GSI.
Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
1998Monitoring system activity for OS-directed dynamic power management.
Luca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò
1998On the optimum design of regulated cascode operational transconductance amplifiers.
Thomas Burger, Qiuting Huang
1998Optimizing the DRAM refresh count for merged DRAM/logic LSIs.
Taku Ohsawa, Koji Kai, Kazuaki J. Murakami
1998Partial bus-invert coding for power optimization of system level bus.
Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
1998Power and performance tradeoffs using various caching strategies.
R. Iris Bahar, Gianluca Albera, Srilatha Manne
1998Power calculation and modeling in deep submicron.
Jay Abraham
1998Power consumption of parallel spread spectrum correlator architectures.
Won Namgoong, Teresa H. Meng
1998Power dissipated by CMOS gates driving lossless transmission lines.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998Power distribution in high-performance design.
Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel
1998Power exploration for dynamic data types through virtual memory management refinement.
Julio Leao da Silva Jr., Francky Catthoor, Diederik Verkest, Hugo De Man
1998Power invariant vector compaction based on bit clustering and temporal partitioning.
Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano
1998Power-delay tradeoffs for radix-4 and radix-8 dividers.
Alberto Nannarelli, Tomás Lang
1998Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998
Anantha P. Chandrakasan, Sayfe Kiaei
1998Recent developments in high integration multi-standard CMOS transceivers for personal communication systems.
Jacques Christophe Rudell, Jia-Jiunn Ou, R. Sekhar Narayanaswami, George Chien, Jeffrey A. Weldon, Li Lin, King-Chun Tsai, Luns Tee, Kelvin Khoo, Danelle Au, Troy Robinson, Danilo Gerna, Masanori Otsuka, Paul R. Gray
1998Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.
Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
1998Stream synthesis for efficient power simulation based on spectral transforms.
Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
1998System-level power estimation and optimization.
Luca Benini, Robin Hodgson, Polly Siegel
1998The energy complexity of register files.
Victor V. Zyuban, Peter M. Kogge
1998The impact of data characteristics and hardware topology on hardware selection for low power DSP.
Gareth Keane, Jonathan R. Spanier, Roger F. Woods
1998The logarithmic number system for strength reduction in adaptive filtering.
John R. Sacha, Mary Jane Irwin
1998The petrol approach to high-level power estimation.
Rafael Peset Llopis, Kees Goossens
1998The simulation and evaluation of dynamic voltage scaling algorithms.
Trevor Pering, Thomas D. Burd, Robert W. Brodersen
1998Theoretical bounds for switching activity analysis in finite-state machines.
Diana Marculescu, Radu Marculescu, Massoud Pedram
1998Towards the capability of providing power-area-delay trade-off at the register transfer level.
Chun-Hong Chen, Chi-Ying Tsui
1998True single-phase energy-recovering logic for low-power, high-speed VLSI.
Suhwan Kim, Marios C. Papaefthymiou
1998Voltage scheduling problem for dynamically variable voltage processors.
Tohru Ishihara, Hiroto Yasuura