ISCAS C

170 papers

YearTitle / Authors
1993200 Mega Pixel Rate IDCT Processor for HDTVC Applications.
Chan S. Kim, Sang W. Song, Man Y. Kim, Young T. Han, Sang A. Kang, Bang W. Lee
1993A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.
James B. Kuo, Hung-Pin Chen, H. J. Huang
1993A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform.
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1993A Class of Zero Wasted Area Floorplan for VLSI Design.
Kai Wang, Wai-Kai Chen
1993A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.
Mark W. Mao, B. Y. Chen, James B. Kuo
1993A Compact Array Processor Based on Self-timed Simultaneous Bidirectional Signalling.
Ghassan Y. Yacoub, Tarun Soni, Walter H. Ku
1993A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
1993A Fast Parallel Algorithm for Slicing Floorplans.
Cheng-Hsi Chen, Ioannis G. Tollis
1993A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic.
Klaus Gaedke, Jens Franzen, Peter Pirsch
1993A Functional-level Testability Evaluation Using a New M-Testability.
Mohamed Jamoussi, Bozena Kaminska
1993A Fuzzy C-means Clustering Placement Algorithm.
M. Razaz
1993A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders.
Emmanuel Boutillon, Nicolas Demassieux
1993A Graph Partitioning Problem for Multiple-chip Design.
Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
1993A Heursitsic Global Optimization Algorithm and Its Application to CMOS Circuit Variability Minimization.
Ming Qu, M. A. Styblinski
1993A Hierarchical Multiprocessor Achitecture for Video Coding Applications.
Peter Pirsch, Winfried Gehrke, Richard Hoffer
1993A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm.
Hakim Khali, Jean-Louis Houle, Yvon Savaria
1993A High Throughput Systolic Design for QR Algorithm.
Jiann-Jenn Wang, Chein-Wei Jen
1993A High Throughput-Rate Architecture for 8*8 2-D DCT.
Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu
1993A Logic-enhanced Memory for Digital Data Recovery Circuits.
Kenneth J. Schultz, P. Glenn Gulak
1993A Method for Improving the Efficiency of Simulating Large Electronic Circuits.
H. Song, Dileep A. Divekar, L. Mills, P. Wang
1993A Monolithic Asynchronous Sample-Rate Converter for Digital Audio.
Robert Adams, Tom Kwan
1993A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation.
K. J. Ray Liu, An-Yeu Wu
1993A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
1993A New Approach to Reconfigure Faulty Systolic Array.
Stephen P. S. Lam
1993A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM.
Young-Hyun Jun, Weon-Hwa Jeong, Jong-Hoon Park, Tae-Hoon Kim, Seong-Wook Kim, Jae-sik Lee, Seong-Jin Jang, Chang-Man Khang, Hee-Gook Lee
1993A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
1993A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays.
Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa
1993A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing.
N. S. Nagaraj
1993A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout.
Nasir-ud-Din Gohar, Peter Y. K. Cheung
1993A New Strategy for Library-independent Layout Design.
Achim G. Hoffmann
1993A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits.
Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi
1993A Parallel Force Direct Based VLSI Standard Cell Placement Algorithm.
E. I. Horvath
1993A Parallel SONET Scrambler/Descrambler Architecture.
Srini W. Seetharam, Gary J. Minden, Joseph B. Evans
1993A Performance-driven Approach to the High-level Synthesis of DSP Algorithms.
Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai
1993A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.
Naresh R. Shanbhag, Keshab K. Parhi
1993A Programmable Video Signal Multi-processor for HDTV Signals.
Nobuyuki Yagi, Kazuo Fukui, Kazumasa Enami, Nobuyuki Sasaki, Hidetaka Saitou, Yuji Konno, Ryuichiro Tomita
1993A Single Chip High Data Rate QPSK Demodulator.
D. Wagner, Subhash C. Kwatra, Mohsin M. Jamali
1993A Single Chip Lempel-Ziv Data Compressor.
Belle W. Y. Wei, Richard Tarver, Jong-Seop Kim, Kevin Ng
1993A Spatial Schur Type LS Algorithm and Its Pyramid Systolic Array Implementation.
Xiaqi Liu, Hong Fan
1993A Systematic Approach of Statistical Modeling and Its Application to CMOS Circuits.
Jian Chen, M. A. Styblinski
1993A Systematic Method for Nonlinear Analysis of a Class of FET Circuits.
Carlos A. Losada, David G. Haigh, Paul M. Radmore
1993A Systematic Methodology for Designing Multilevel Systolic Architectures.
Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis
1993A Technique to Improve the Convergency Speed of Relaxation-based Simulations in Tightly Coupled Circuits.
Richard M. M. Chen, Xing Dong Jia
1993A Two-pole Circuit Model for VLSI High-speed Interconnection.
Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong
1993A Universal BIST Methodology for Interconnects.
Chiyuan Chang, Chauchin Su
1993A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
1993Adaptive Hierarchical Multi-objective Fuzzy Optimization for Circuit Design.
B. R. S. Rodrigues, M. A. Styblinski
1993An Accurate AC Characteristic Table Look-up Model for VLSI Analog Circuits Simulation Applications.
Dae-Hyung Cho, S. M. Kang
1993An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers.
Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross
1993An Algorithm for the Calculation of Generalized Walsh Transform of Boolean Functions.
Bogdan J. Falkowski
1993An Architecture for Intermediate Area-time Complexity Multiplier.
Farhad Fuad Islam, Keikichi Tamaru
1993An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.
Malgorzata Chrzanowska-Jeske, Steffen Goller, Ingo Schäfer
1993An Efficient Global Search Algorithm for Test Generation.
Abdel-Fattah Yousif, Jun Gu
1993An Efficient Tolerance Design Procedure for Yield Maximization Using Optimzation Techniques and Neural Network.
Richard M. M. Chen, Wilson W. Chan
1993An Examination of Feedback Bridging Faults in Digital CMOS Circuits.
Bernd K. Koch, Klaus D. Müller-Glaser
1993An Expandable Chip Desing for Gray-scale Morphological Operations.
Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu
1993An Improved Random Walk Approach for Yield Optimization.
Songxin Qi, Quanrang Yang
1993Analog Design Optimization : A Case Study.
Jorge Chávez Orzáez, Miguel Angel Aguirre Echánove, Antonio Jesús Torralba Silgado
1993Analog Synthesis from Behavioural Descriptions.
Subbarao Somanchi, Mark L. Manwaring
1993Arbitrarily Sized Cell Placement by Self-organizing Neural Networks.
Ray-I Chang, Pei-Yung Hsiao
1993Architecture and VLSI Design of a VLSI Neural Signal Processor.
Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder
1993Automatic Design of Transparent Standard Cells with TRANSCAD II.
Oskar Anton, Karol Doerffer, Dieter A. Mlynski
1993Automatic Generation of Transistor Stacks for CMOS Analog Layout.
Valentino Liberali, Enrico Malavasi, Davide Pandini
1993Block Sequential CORDIC Architectures.
Matthias Sauer, Ernst G. Bernard, Josef A. Nossek
1993Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs.
K. Wayne Current, James F. Parker, Wes Hardaker
1993Bounds for Distributed Parameter Trees.
Corneliu A. Marinov, Pekka Neittaanmäki
1993CORDIC Based Pipeline Architecture for All-pass Filters.
Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis
1993Calculation of Rademacher-Walsh Spectral Coefficients for Systems of Completely and Incompletely Specified Boolean Functions.
Bogdan J. Falkowski
1993Circuit Partitioning Using a Tabu Search Approach.
Shawki Areibi, Anthony Vannelli
1993Clock Distribution Design in VLSI Circuits. An Overview.
Eby G. Friedman
1993Codebook Generation and Search Algorithm for Vector Quantization Using Arbitrary Hyperplanes.
S. C. Chan, Chi-Wah Kok, S. W. Chau
1993Compact and Fast Multiplier Using Dual Array Tree Structure.
Min C. Park, Bang W. Lee, Gwang Moon Kim, Dong H. Kim
1993Computer-aided Sensitivity Analysis of Transistor Microwave Oscillators.
Nebil Tanzi, Thomas T. Y. Wong
1993Data-stationary Controller for 32-bit Application-specific RISC.
Moon Key Lee, Byeong Yoon Choi, Kwang Yub Lee, Seong Ho Lee
1993Design Methodology of VLSI with Multiple Valued Logic.
Stephen Summerfield
1993Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering.
Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi
1993Difference Model Approach for the Transient Simulation of Transmission Lines.
Dimitri Kuznetsov, José E. Schutt-Ainé
1993Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem.
Crystal J. Su, Kai-Pui Lam
1993Double Edge Triggered Devices: Speed and Power Considerations.
Razak Hossain, Leszek D. Wronski, Alexander Albicki
1993Dynamic Partitioning for Concurrent Waveform Relaxation-based Circuit Simulation.
Lena Peterson, Sven Mattisson
1993ECCSyn: a Synthesis Tool for ECC Circuits.
Chauchin Su, Jyrghong Wang
1993Easily Testable PLA-based FSMS.
Maria J. Avedillo, José M. Quintana, José L. Huertas
1993Efficient Floorplan Enumeration Using Dynamic Programming.
Sharat Prasad, Paul Kollaritsch, P. Anirudhan, D. K. Hwang, Steve Lusky, R. Farrow
1993Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model.
Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
1993Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.
Soo Young Lee, Kewal K. Saluja
1993Efficient Variable Ordering Heuristics for Shared ROBDD.
Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
1993Efficient and Robust Path Tracing Algorithm for DC Convergence Problem.
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
1993Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.
Weitong Chuang, Ibrahim N. Hajj
1993Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits.
Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon
1993Feasible Region Approximation Using Convex Polytopes.
Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
1993Finite Word-length Effects on Arithmetic Codes.
Shawmin Lei
1993Flexible Mixed-mode and Mixed-level Simulation.
Hans Fleurkens, Pim H. W. Buurman
1993Folded VLSI Architectures for Discrete Wavelet Transforms.
Keshab K. Parhi, Takao Nishitani
1993Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems.
Seon Wook Kim, Thanos Stouraitis, Alexander Skavantzos
1993Fully-digital Testability of a High-speed Conversion System.
João C. Vital, José E. Franca, Nuno S. Silva
1993Functional Testing and Constrained Synthesis of Sequential Architectures.
Giacomo Buonanno, Franco Fummi, Donatella Sciuto
1993Functional Text Pattern Generation for Asynchronous Circuits.
Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu
1993Functional Verification of ECL Circuits Including Voltage Regulators.
Elizabeth J. Brauer, Sung-Mo Kang
1993Fuzzy Logic Functions Synthesis - A CMOS Current Mirror Based Solution.
Laurent Lemaitre, Marek J. Patyra
1993GEM: A Geometric Algorithm for Scheduling.
Salil Raje, Majid Sarrafzadeh
1993Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.
Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
1993Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort.
Kumar Venkat
1993Generation of Chain-coded Contours and Contours Inclusion Relationship Under Multiprocessor Environment.
Clifford Sze-Tsan Choy, Wan-Chi Siu
1993Hierarchical Symbolic Cirucit Analysis of Large-scale Networks on Multi-processor Systems.
Marwan M. Hassoun, Prakash Atawale
1993High Performance Graphics on a SIMD Linear Processor Array.
Laurent Letellier, Didier Juvin, Jean-Luc Basille, Jean Rebillat
1993High Speed RLS Using Scaled Tangent Rotations (STAR).
Kalavai J. Raghunath, Keshab K. Parhi
1993High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage.
Takayasu Sakurai
1993Initiability: A Measure of Sequential Testability.
Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria
1993Integration of Clock Skew and Register Delays into a Retiming Algorithm.
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
1993Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
Ian G. Harris, Alex Orailoglu
1993Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies.
Perng-Shyong Lin, Charles A. Zukowski
1993KLaGen - A Generator of Static CMOS-cell Layout from Circuit Schematics.
Karol Doerffer, Attila T. Téby, Oskar Anton, Dieter A. Mlynski
1993Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.
Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang
1993Loop List Scheduler for DSP Algorithms under Resource Consraints.
Ching-Yi Wang, Keshab K. Parhi
1993Low Latency Architectures for Wave Digital Filters.
D. K. Harris-Dowsett, Stephen Summerfield
1993Methodology for the Design of Signed-digit DSP Processors.
Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
1993Minimum Density Interconneciton Trees.
Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1993Modeling Interconnections with Nonlinear Discontinuities.
José E. Schutt-Ainé, Kyung-soo Oh
1993Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm.
Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae
1993New Concepts for the Design of Carry Lookahaead Adders.
Zhongde Wang, Graham A. Jullien, William C. Miller, June Wang
1993New Model Parameter Extraction Environment for the Submicron Circuit Models.
Chang-Hoon Choi, Jin-Kyu Park, Yeong-Gil Kim, Kyung-Ho Kim, Sang-Hoon Lee
1993Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate.
Jue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen
1993On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.
Kaushik Roy
1993On Multiple Fault Detection of Parity Checkers.
Cheng-Juei Wu, Wen-Ben Jone
1993On Parallel Symbolic Analysis of Large Networks and Systems.
Tadashi Matsumoto, Tetsuya Sakabe, Kohkichi Tsuji
1993On the Comparison Between Architectures for the Implementation of Distributed Arithmetic.
Stefan Wolter, Andreas Schubert, Holger Matz, Rainer Laur
1993On the Performance of Augmented Signature Testing.
Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson
1993On the Resetability of Synchronous Sequential Circuits.
Antonio Lioy, Massimo Poncino
1993On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits.
Tam Anh Chu
1993Parallel Implementation of a Cut and Paste Maze Routing Algorithm.
H. Kumar, Magdy A. Bayoumi, Akhilesh Tyagi, Nam Ling, R. Kalyan
1993Parallel Random Sampling with Multiprocessor System.
K. C. Lo, Alan Purvis
1993Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
Mohamed Nekili, Yvon Savaria
1993Parallel Solution of Symmetric Banded Systems on Transputers.
Fida H. Chishti, Anthony R. Clare, Moe Razaz
1993Parallel Time Domain Analysis and Optimization of Distributed VLSI Interconnects.
J. Richard Griffith, Qi-Jun Zhang, Michel S. Nakhla
1993Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits.
Ion Constatin Tesu, Florentin Dartu
1993Processor Allocation in Faulty Hypercube Multiprocessors.
Suresh Rai, Jerry L. Trahan, Thomas Smailus
1993Propagation Delay in RLC Interconnection Networks.
D. S. Gao, Dian Zhou
1993Quadrisectioning Based Placement with a Normalized Mean Field Neural Network.
M. Kemal Unaltuna, Vijay Pitchumani
1993RTL Synthesis for Systolic Arrays.
William Robertson, S. Periyalwar, William J. Phillips
1993Rank-order Filtering Algorithms: A Comparison of VLSI Implementations.
J. David Narkiewicz, Wayne P. Burleson
1993Reducing Message Logging Overhead for Log-based Recovery.
Yi-Min Wang
1993Reducing the Physical Design Cycle by Means of Topological Placement with Hard Timing Restraints.
Bernd E. Freier
1993Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
Hong-Yi Huang, Chung-Yu Wu
1993Resynthesis and Retiming of Synchronous Sequential Cirucits.
Samir Lejmi, Bozena Kaminska, Edouard Wagneur
1993SALSE II: A Fast Transformational Scheduler for High-level Synthesis.
Michael R. Rhinehart, John A. Nestor
1993SCANSA: A Computer Program for the Statistical Analysis of Switched Capacitor Networks.
Domenico Biey, Mario Biey, Maurizio Molinaro
1993SENSATION: A New Environment for Automatic Circuit Optimization and Statistical Analysis.
Yeong-Gil Kim, Jai-Hoon Lee, Kyung-Ho Kim, Sang-Hoon Lee
1993Scheduling of a Control and Data Flow Graph.
Said Amellal, Bozena Kaminska
1993Signal Routing with Temporal Constraints.
P. R. Mukund, V. Mukund, Charles E. Noon
1993Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis.
Ruchir Puri, Jun Gu
1993Simulation of Networks with Inconsistent Initial Conditions.
Jirí Vlach, Ajoy Opal, Jacek Wojciechowski
1993Single Processor Design for 2-D Wiener Filter.
Kuei-Ann Wen, Shihn-Cheng Chen, Jo-Tan Yao
1993Solving Gate-Matrix Layout Problems by Simulated Evolution.
Yu Hen Hu, Chi-Yu Mao
1993Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks.
Qiuting Huang
1993Speeding Design Centering By Reusing Simulated Data.
Xiangming Xiao, Robert Spence
1993Static Allocation of a Task Tree onto a Linear Array.
Tsuyoshi Kawaguchi
1993Superpipelined Adder Designs.
Ishaq H. Unwala, Earl E. Swartzlander Jr.
1993Symbolic Precompilation of Piecewise-linear Behavioral Models for Efficient Simulation of Dual Time Scale Systems.
Christopher M. Wolff, Jung-hui Cheng
1993Systolic Array for 2-D Circular Convolution Using the Chinese Remainder Theorem.
L. Wang, Iiro Hartimo
1993Test Generation for BiCMOS Circuits.
Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya
1993The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.
Brian S. Cherkauer, Eby G. Friedman
1993The Use of Symbolic-numerical Methods for Electronic Circuit Analysis.
Roman V. Dmytryshyn
1993Time Efficient Method for MOS Circuit Extraction.
Karol Doerffer, Oskar Anton, Dieter A. Mlynski
1993Time- and Order-recursive Estimation of Higher Order Moments in a Linear Array.
Haris M. Stellakis, Elias S. Manolakos
1993Timing-, Heat- and Area-driven Placement Using Self-organizing Semantic Maps.
Chen-Xiong Zhang
1993Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC.
Michael F. Toner, Gordon W. Roberts
1993VLSI Implementation of an Associative Memory Using Temporal Relations.
Hazem H. Ali, Mona E. Zaghloul
1993Video Decimator Design Using A Systolic Array.
Scott T. Campbell, Soon Myoung Chung
1993Yield Optimzation of Analog MOS Integrated Including Transistor Mismatch.
Hua Su, Mohammed Ismail, Christopher Michael
1993m3D: A Multidimensional Dynamic Configurable Router.
Charles Wiley, K. M. Lau, Stephen A. Szygenda