ISCA A*

39 papers

YearTitle / Authors
1991Adaptive Storage Management for Very Large Virtual/Real Storage Systems.
Toyohiko Kagimasa, Kikuo Takahashi, Toshiaki Mori, Seiichi Yoshizumi
1991An Architecture for Software-Controlled Data Prefetching.
Alexander C. Klaiber, Henry M. Levy
1991An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks.
Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu
1991Branch History Table Prediction of Moving Target Branches due to Subroutine Returns.
David R. Kaeli, Philip G. Emma
1991Chaos Router: Architecture and Performance.
Smaragda Konstantinidou, Lawrence Snyder
1991Classification and Performance Evaluation of Instruction Buffering Techniques.
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai
1991Comparative Evaluation of Latency Reducing and Tolerating Techniques.
Anoop Gupta, John L. Hennessy, Kourosh Gharachorloo, Todd C. Mowry, Wolf-Dietrich Weber
1991Comparison of Hardware and Software Cache Coherence Schemes.
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon
1991Data Prefetching in Multiprocessor Vector Cache Memories.
John W. C. Fu, Janak H. Patel
1991Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks.
Xiaola Lin, Lionel M. Ni
1991Detecting Data Races on Weak Memory Systems.
Sarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer
1991Dynamic Base Register Caching: A Technique for Reducing Address Bus Width.
Matthew K. Farrens, Arvin Park
1991Evaluation of Memory System Extensions.
Kai Li, Karin Petersen
1991Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques.
Stephen W. Melvin, Yale N. Patt
1991Flexible Register Management for Sequential Programs.
Donna J. Quammen, D. Richard Miller
1991GT-EP: A Novel High-Performance Real-Time Architecture.
Wei Siong Tan, H. Russ, Cecil O. Alford
1991High Performance Interprocessor Communication through Optical Wavelength Division Multiple Access Channels.
Patrick W. Dowd
1991IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
1991IXM2: A Parallel Associative Processor.
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu
1991Implementing a Cache for a High-Performance GaAs Microprocessor.
Kunle Olukotun, Trevor N. Mudge, Richard B. Brown
1991Instruction Level Profiling and Evaluation of the IBM/6000.
Chriss Stephens, Bryce Cogswell, John Heinlein, Gregory Palmer, John Paul Shen
1991Modeling and Measurement of the Impact of Input/Output on System Performance.
Janaki Akella, Daniel P. Siewiorek
1991Modeling the Performance of Limited Pointers Directories for Cache Coherence.
Richard Simoni, Mark Horowitz
1991Multi-Threaded Vectorization.
Tzi-cker Chiueh
1991Multithreading: A Revisionist View of Dataflow Architectures.
Gregory M. Papadopoulos, Kenneth R. Traub
1991OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications.
Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota
1991On the Validity of Trace-Driven Simulation for Multiprocessors.
Eric J. Koldinger, Susan J. Eggers, Henry M. Levy
1991Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event Traces.
C. W. Oehlrich, Andreas Quick
1991Performance Prediction and Tuning on a Multiprocessor.
Robert T. Dimpsey, Ravishankar K. Iyer
1991Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991
Zvonko G. Vranesic
1991Pseudo-Randomly Interleaved Memory.
B. Ramakrishna Rau
1991Race-Free Interconnection Networks and Multiprocessor Consistency.
Anders Landin, Erik Hagersten, Seif Haridi
1991Reducing Memory Contention in Shared Memory Multiprocessors.
David T. Harper III
1991Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time Applications.
Shridhar B. Shukla, Dharma P. Agrawal
1991Single Instruction Stream Parallelism is Greater Than Two.
Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
1991Strategies for Achieving Improved Processor Throughput.
Matthew K. Farrens, Andrew R. Pleszkun
1991The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy.
David G. Bradlee, Susan J. Eggers, Robert R. Henry
1991The SNAP-1 Parallel AI Prototype.
Ronald F. DeMara, Dan I. Moldovan
1991Virtualizing the VAX Architecture.
Judith S. Hall, Paul T. Robinson