ISCA A*

47 papers

YearTitle / Authors
19892-D SIMD Algorithms in the Perfect Shuffle Networks.
Yosi Ben-Asher, David Egozi, Assaf Schuster
1989A Cache Consistency Protocol for Multiprocessors with Multistage Networks.
Per Stenström
1989A Dynamic Storage Scheme for Conflict-Free Vector Access.
David T. Harper III, Darel A. Linebarger
1989A High Performance Prolog Processor with Multiple Function Units.
Ashok Singhal, Yale N. Patt
1989A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine.
Manuel L. Anido, David J. Allerton, Ed Zaluska
1989A Type Driven Hardware Engine for Prolog Clause Retrieval over a Large Knowledge Base.
Kam-Fai Wong, M. Howard Williams
1989Achieving High Instruction Cache Performance with an Optimizing Compiler.
Wen-mei W. Hwu, Pohua P. Chang
1989Adaptive Backoff Synchronization Techniques.
Anant Agarwal, Mathews Cherian
1989An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors.
Shlomo Weiss
1989An Architecture Framework for Application-Specific and Scalable Architectures.
Johannes M. Mulder, Robert J. Portier, A. Srivastava, R. in 't Velt
1989An Architecture of a Dataflow Single Chip Processor.
Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba
1989Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures.
Dipak Ghosal, Satish K. Tripathi, Laxmi N. Bhuyan, Hong Jiang
1989Analysis of Vector Access Performance on Skewed Interleaved Memory.
Chuen-Liang Chen, Chung-Kai Liao
1989Architectural Mechanisms to Support Sparse Vector Processing.
Roland N. Ibbett, T. M. Hopkins, K. I. M. McKinnon
1989Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU.
Norman P. Jouppi
1989Can Dataflow Subsume von Neumann Computing?
Rishiyur S. Nikhil
1989Characteristics of Performance-Optimal Multi-Level Cache Hierarchies.
Steven A. Przybylski, Mark Horowitz, John L. Hennessy
1989Comparing Software and Hardware Schemes For Reducing the Cost of Branches.
Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
1989Constructing Replicated Systems Using Processors with Point-to-Point Communication Links.
Paul D. Ezhilchelvan, Santosh K. Shrivastava, Alan Tully
1989Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures.
Atsuhiro Goto, Akira Matsumoto, Evan Tick
1989Evaluating the Performance of Four Snooping Cache Coherency Protocols.
Susan J. Eggers, Randy H. Katz
1989Exploiting Data Parallelism in Signal Processing on a Data Flow Machine.
Peter Nitezki
1989Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results.
Wolf-Dietrich Weber, Anoop Gupta
1989High Performance Communications in Processor Networks.
Chris R. Jesshope, P. R. Miller, Jay T. Yantchev
1989Improving Performance of Small On-Chip Instruction Caches.
Matthew K. Farrens, Andrew R. Pleszkun
1989Inexpensive Implementations of Set-Associativity.
Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill
1989Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors.
Marco Annaratone, Claude Pommerell, Roland Rühl
1989Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks.
Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan
1989KCM: A Knowledge Crunching Machine.
Hans Benker, Jean-Michel Beacco, Sylvie Bescos, Michel Dorochevsky, Thomas Jeffré, Anita Pohlmann, Jacques Noyé, Bruno Poterie, Alan P. Sexton, Jean-Claude Syre, Oliver Thibault, Günter Watzlawik
1989Logic Simulation on Massively Parallel Architectures.
Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
1989Multi-level Shared Caching Techniques for Scalability in VMP-M/C.
David R. Cheriton, Hendrik A. Goosen, Patrick D. Boyle
1989Multiple vs. Wide Shared Bus Multiprocessors.
Andy Hopper, Alan Jones, Dimitris Lioupis
1989On Data Synchronization for Multiprocessors.
Hong-Men Su, Pen-Chung Yew
1989Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy.
Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy
1989Perfect Latin Squares and Parallel Array Access.
Kichul Kim, Viktor K. Prasanna
1989Performance Measurements on a Commercial Multiprocessor Running Parallel Code.
Marco Annaratone, Roland Rühl
1989Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989
Jean-Claude Syre
1989R256: A Research Parallel Processor for Scientific Computation.
Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh
1989Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto
1989S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP.
M. Morioka
1989SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.
Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita
1989Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache.
David A. Wood, Randy H. Katz
1989Systematic Hardware Adaptation of Systolic Algorithms.
Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
1989Task Migration in Hypercube Multiprocessors.
Ming-Syan Chen, Kang G. Shin
1989The Epsilon Dataflow Processor.
V. Gerald Grafe, George S. Davidson, Jamie E. Hoch, V. P. Holmes
1989The Impact of Code Density on Instruction Cache Performance.
Peter Steenkiste
1989Using Feedback to Control Tree Saturation in Multistage Interconnection Networks.
Steven L. Scott, Gurindar S. Sohi