ISCA A*

49 papers

YearTitle / Authors
201037th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France
André Seznec, Uri C. Weiser, Ronny Ronen
2010A case for FAME: FPGA architecture model execution.
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson
2010A dynamically configurable coprocessor for convolutional neural networks.
Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi
2010An integrated GPU power and performance model.
Sunpyo Hong, Hyesoon Kim
2010An intra-chip free-space optical interconnect.
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore
2010Aérgia: exploiting packet latency slack in on-chip networks.
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2010Cohesion: a hybrid memory model for accelerators.
John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel
2010ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations.
Brandon Lucia, Luis Ceze, Karin Strauss
2010Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races.
Brandon Lucia, Luis Ceze, Karin Strauss, Shaz Qadeer, Hans-Juergen Boehm
2010Data marshaling for multi-core architectures.
M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
2010Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU.
Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey
2010Dynamic warp subdivision for integrated branch and memory divergence tolerance.
Jiayuan Meng, David Tarjan, Kevin Skadron
2010Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.
Enric Herrero, José González, Ramon Canal
2010Energy proportional datacenter networks.
Dennis Abts, Michael R. Marty, Philip M. Wells, Peter Klausler, Hong Liu
2010Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz
2010Evolution of thread-level parallelism in desktop applications.
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner
2010Forwardflow: a scalable core for power-constrained CMPs.
Dan Gibson, David A. Wood
2010High performance cache replacement using re-reference interval prediction (RRIP).
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer
2010IVEC: off-chip memory integrity protection for both security and reliability.
Ruirui C. Huang, G. Edward Suh
2010Improving the future by examining the past.
Charles P. Thacker
2010LReplay: a pending period based deterministic replay scheme.
Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu
2010Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.
Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li
2010Modeling critical sections in Amdahl's law and its implications for multicore design.
Stijn Eyerman, Lieven Eeckhout
2010Morphable memory system: a robust architecture for exploiting multi-level phase change memories.
Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis
2010Moving the needle, computer architecture research in academe and industry.
William J. Dally
2010Necromancer: enhancing system throughput by animating dead cores.
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
2010NoHype: virtualized cloud infrastructure without the virtualization.
Eric Keller, Jakub Szefer, Jennifer Rexford, Ruby B. Lee
2010RETCON: transactional repair without replay.
Colin Blundell, Arun Raghavan, Milo M. K. Martin
2010Re-architecting DRAM memory systems with monolithically integrated silicon photonics.
Scott Beamer, Chen Sun, Yong-jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic
2010Reducing cache power with low-cost, multi-bit error-correcting codes.
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2010Relax: an architectural framework for software recovery of hardware faults.
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam
2010Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.
Xiaochen Guo, Engin Ipek, Tolga Soyata
2010Rethinking DRAM design and organization for energy-constrained multi-cores.
Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2010Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping.
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
2010Sentry: light-weight auxiliary memory access control.
Arrvindh Shriraman, Sandhya Dwarkadas
2010Shared caches in multicores: the good, the bad, and the ugly.
Mary Jane Irwin
2010SieveStore: a highly-selective, ensemble-level disk cache for cost-performance.
Timothy Pritchett, Mithuna Thottethodi
2010Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.
Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy
2010The impact of management operations on the virtualized datacenter.
Vijayaraghavan Soundararajan, Jennifer M. Anderson
2010The rebirth of neural networks.
Olivier Temam
2010The virtual write queue: coordinating DRAM and last-level cache policies.
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
2010Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications.
Janghaeng Lee, Haicheng Wu, Madhumitha Ravichandran, Nathan Clark
2010Timetraveler: exploiting acyclic races for optimizing memory race recording.
Gwendolyn Voskuilen, Faraz Ahmad, T. N. Vijaykumar
2010Translation caching: skip, don't walk (the page table).
Thomas W. Barr, Alan L. Cox, Scott Rixner
2010Understanding sources of inefficiency in general-purpose chips.
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz
2010Use ECP, not ECC, for hard failures in resistive memories.
Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger
2010Using hardware vulnerability factors to enhance AVF analysis.
Vilas Sridharan, David R. Kaeli
2010Web search using mobile cores: quantifying and mitigating the price of efficiency.
Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid
2010WiDGET: Wisconsin decoupled grid execution tiles.
Yasuko Watanabe, John D. Davis, David A. Wood