ISCA A*

28 papers

YearTitle / Authors
200229th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA
Yale N. Patt, Dirk Grunwald, Kevin Skadron
2002A Large, Fast Instruction Window for Tolerating Cache Misses.
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
2002A Scalable Instruction Queue Design Using Dependence Chains.
Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt
2002An Instruction Set and Microarchitecture for Instruction Level Distributed Processing.
Ho-Seop Kim, James E. Smith
2002Avoiding Initialization Misses to the Heap.
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
2002Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.
André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
2002Detailed Design and Evaluation of Redundant Multithreading Alternatives.
Shubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt
2002Difficult-Path Branch Prediction Using Subordinate Microthreads.
Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz
2002Drowsy Caches: Simple Techniques for Reducing Leakage Power.
Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, Trevor N. Mudge
2002Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines.
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic
2002Efficient Dynamic Scheduling Through Tag Elimination.
Dan Ernst, Todd M. Austin
2002Experiences with VI Communication for Database Storage.
Yuanyuan Zhou, Kai Li, Angelos Bilas, Suresh Jagannathan, Cezary Dubnicki, James Philbin
2002Going the Distance for TLB Prefetching: An Application-Driven Study.
Gokul B. Kandiraju, Anand Sivasubramaniam
2002Implementing Optimizations at Decode Time.
Ilhyun Kim, Mikko H. Lipasti
2002Increasing Processor Performance by Implementing Deeper Pipelines.
Eric Sprangle, Doug Carmean
2002Managing Multi-Configuration Hardware via Dynamic Working Set Analysis.
Ashutosh S. Dhodapkar, James E. Smith
2002Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors.
Anoop Iyer, Diana Marculescu
2002Queue Pair IP: A Hybrid Architecture for System Area Networks.
Philip Buonadonna, David E. Culler
2002ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors.
Milos Prvulovic, Josep Torrellas, Zheng Zhang
2002SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
2002Slack: Maximizing Performance Under Technological Constraints.
Brian A. Fields, Rastislav Bodík, Mark D. Hill
2002Speculative Dynamic Vectorization.
Alex Pajuelo, Antonio González, Mateo Valero
2002Tarantula: A Vector Extension to the Alpha Architecture.
Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
2002The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
2002The Optimum Pipeline Depth for a Microprocessor.
Allan Hartstein, Thomas R. Puzak
2002Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior.
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
2002Transient-Fault Recovery Using Simultaneous Multithreading.
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
2002Using a User-Level Memory Thread for Correlation Prefetching.
Yan Solihin, Josep Torrellas, Jaejin Lee