| 2000 | 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada Alan D. Berenbaum, Joel S. Emer |
| 2000 | A fully associative software-managed cache design. Erik G. Hallnor, Steven K. Reinhardt |
| 2000 | A hardware mechanism for dynamic extraction and relayout of program hot spots. Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu |
| 2000 | A scalable approach to thread-level speculation. J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry |
| 2000 | Allowing for ILP in an embedded Java processor. Ramesh Radhakrishnan, Deependra Talla, Lizy Kurian John |
| 2000 | An embedded DRAM architecture for large-scale spatial-lattice computations. Norman Margolus |
| 2000 | Architectural support for scalable speculative parallelization in shared-memory multiprocessors. Marcelo H. Cintra, José F. Martínez, Josep Torrellas |
| 2000 | CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee |
| 2000 | Circuits for wide-window superscalar processors. Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami |
| 2000 | Clock rate versus IPC: the end of the road for conventional microarchitectures. Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger |
| 2000 | Completion time multiple branch prediction for enhancing trace cache performance. Ryan N. Rakvic, Bryan Black, John Paul Shen |
| 2000 | Early load address resolution via register tracking. Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen |
| 2000 | Energy-driven integrated hardware-software optimizations using SimplePower. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye |
| 2000 | HLS: combining statistical and symbolic simulation to guide microprocessor designs. Mark Oskin, Frederic T. Chong, Matthew K. Farrens |
| 2000 | Instruction path coprocessors. Yuan C. Chou, John Paul Shen |
| 2000 | Lx: a technology platform for customizable VLIW embedded processing. Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred Homewood |
| 2000 | Memory access scheduling. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens |
| 2000 | Multiple-banked register file architectures. José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham |
| 2000 | On the value locality of store instructions. Kevin M. Lepak, Mikko H. Lipasti |
| 2000 | Performance analysis of the Alpha 21264-based Compaq ES40 system. Zarka Cvetanovic, Richard E. Kessler |
| 2000 | Piranha: a scalable architecture based on single-chip multiprocessing. Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese |
| 2000 | Recency-based TLB preloading. Ashley Saulsbury, Fredrik Dahlgren, Per Stenström |
| 2000 | Reconfigurable caches and their application to media processing. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi |
| 2000 | Selective, accurate, and timely self-invalidation using last-touch prediction. An-Chow Lai, Babak Falsafi |
| 2000 | Smart Memories: a modular reconfigurable architecture. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz |
| 2000 | Trace preconstruction. Quinn Jacobson, James E. Smith |
| 2000 | Transient fault detection via simultaneous multithreading. Steven K. Reinhardt, Shubhendu S. Mukherjee |
| 2000 | Understanding the backward slices of performance degrading instructions. Craig B. Zilles, Gurindar S. Sohi |
| 2000 | Vector instruction set support for conditional operations. James E. Smith, Greg Faanes, Rabin A. Sugumar |
| 2000 | Wattch: a framework for architectural-level power analysis and optimizations. David M. Brooks, Vivek Tiwari, Margaret Martonosi |