| 2005 | 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France |
| 2005 | A 32-Bit COTS-Based Fault-Tolerant Embedded System. Amir Rajabzadeh |
| 2005 | A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir |
| 2005 | A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. René Kothe, Christian Galke, Heinrich Theodor Vierhaus |
| 2005 | A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. Régis Leveugle |
| 2005 | A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. Bartomeu Alorda, Sebastià A. Bota, Jaume Segura |
| 2005 | A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy |
| 2005 | A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. Andrzej Krasniewski |
| 2005 | A Review of DASIE Code Family: Contribution to SEU/MBU Understanding. Guillaume Hubert, Nadine Buard, Cécile Weulersse, Thierry Carrière, Marie-Catherine Palau, Jean-Marie Palau, Damien Lambert, Jacques Baggio, Frederic Wrobel, Frédéric Saigné, Rémi Gaillard |
| 2005 | A Software Based Online Memory Test for Highly Available Systems. Amandeep Singh, Debashish Bose |
| 2005 | Accumulator-Based Weighted Pattern Generation. Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis |
| 2005 | Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits. Tino Heijmen |
| 2005 | Analyzing the Effectiveness of Fault Hardening Procedures. Piotr Gawkowski, Janusz Sosnowski, B. Radko |
| 2005 | Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes |
| 2005 | Coding Techniques for Low Switching Noise in Fault Tolerant Busses. André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra |
| 2005 | DFT Assisted Built-In Soft Error Resilience. T. M. Mak, Subhasish Mitra, Ming Zhang |
| 2005 | Design for Mitigation of Single Event Effects. Michael Nicolaidis |
| 2005 | Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. Kentaroh Katoh, Abderrahim Doumar, Hideo Ito |
| 2005 | Design of a Self Checking Reed Solomon Encoder. Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2005 | Does It Mean Less Testing for Self Calibrating Design?. T. M. Mak |
| 2005 | Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira |
| 2005 | Efficient Estimation of SEU Effects in SRAM-Based FPGAs. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante |
| 2005 | Electrical Modeling for Laser Testing with Different Pulse Durations. Alexandre Douin, Vincent Pouget, Dean Lewis, Pascal Fouillat, Philippe Perdu |
| 2005 | Evaluation of SET and SEU Effects at Multiple Abstraction Levels. Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert |
| 2005 | Fast, Parallel Two-Rail Code Checker with Enhanced Testability. Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou |
| 2005 | Hardening Techniques against Transient Faults for Asynchronous Circuits. Yannick Monnet, Marc Renaudin, Régis Leveugle |
| 2005 | Heavy Ion Effects on Configuration Logic of Virtex FPGAs. Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi |
| 2005 | How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight. Raoul Velazco, R. Ecoffet, F. Faure |
| 2005 | How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. Nicolas Renaud |
| 2005 | How to Cope with SEU/SET at System Level?. Michel Pignol |
| 2005 | IEEE Computer Society TTTC: Test Technology Technical Council. |
| 2005 | Impact of Soft Error Challenge on SoC Design. Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan |
| 2005 | Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators. Erik Schüler, Luigi Carro |
| 2005 | Integrating BIST Techniques for On-Line SoC Testing. Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda |
| 2005 | Introduction to Fault Attacks on Smartcard. Antoine Lemarechal |
| 2005 | Introduction to the Special Session on Secure Implementations. Régis Leveugle |
| 2005 | Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra |
| 2005 | Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing. Yves Crouzet, Jacques Henri Collet, Jean Arlat |
| 2005 | Modeling Soft-Error Susceptibility for IP Blocks. Robert C. Aitken, Betina Hold |
| 2005 | Modeling of Transients Caused by a Laser Attack on Smart Cards. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache |
| 2005 | On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis |
| 2005 | On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee |
| 2005 | On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. Michele Portolan, Régis Leveugle |
| 2005 | On the Proposition of an EMI-Based Fault Injection Approach. Fabian Vargas, D. L. Cavalcante, Edmundo Gatti, Dárcio Prestes, Daniel Lupi |
| 2005 | On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni |
| 2005 | On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt |
| 2005 | On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel |
| 2005 | On-Line Testing for Secure Implementations: Design and Validation. Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert |
| 2005 | On-Line Testing of Globally Asynchronous Circuits. Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad |
| 2005 | Organizing Committee. |
| 2005 | Overview of Soft Errors Issues in Aerospace Systems. Christian Boléat, Gerard Colas |
| 2005 | Power-Balanced Self Checking Circuits for Cryptographic Chips. Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev |
| 2005 | Process Variation Tolerant Online Current Monitor for Robust Systems. Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy |
| 2005 | Program Committee. |
| 2005 | Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou |
| 2005 | Scrubbing and Partitioning for Protection of Memory Systems. Riccardo Mariani, Gabriele Boschi |
| 2005 | Security Constraints in Integrated Circuits. Laurent Sourgen |
| 2005 | Security Testing for Hardware Products: The Security Evaluations Practice. Alain Merle, Jessy Clédière |
| 2005 | Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy |
| 2005 | Side-Channel Issues for Designing Secure Hardware Implementations. Lejla Batina, Nele Mentens, Ingrid Verbauwhede |
| 2005 | Simulation and Mitigation of Single Event Effects. Lorena Anghel, Michael Nicolaidis |
| 2005 | Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future. Andre L. R. Pouponnot |
| 2005 | Test Generation Methodology for High-Speed Floating Point Adders. George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
| 2005 | Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. Ishwar Parulkar, Robert Cypher |
| 2005 | Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in Microelectronics. Frederic Wrobel |
| 2005 | Welcome. |
| 2005 | Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |