IOLTS C

45 papers

YearTitle / Authors
200410th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal
2004A BIST-based Charge Analysis for Embedded Memories.
Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
2004A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors.
Peter D. Hyde, G. Russell
2004A Hierarchical Self Test Scheme for SoCs.
Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus
2004A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits.
Thomas O'Shea, Ian Andrew Grout
2004A New Code with Reduced EMI and Partial EC Possibilities.
Eberhard Böhl, Elmar Dilger, M. Böhl
2004A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.
A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky
2004A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.
Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
2004A Pragmatic Approach to On-Line Testing.
V. Agarwal
2004A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2004A System for Fault Detection and Reconfiguration of Hardware Based Active Networks.
Nikolaos G. Bartzoudis, Alexandros G. Fragkiadakis, David J. Parish, José Luis Núñez
2004A Technique to Reduce Power and Test Application Time in BIST.
Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
2004Accumulator based Test-per-Scan BIST.
P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos
2004An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets.
Carlos Arthur Lang Lisbôa, Luigi Carro
2004Asynchronous Circuits Sensitivity to Fault Injection.
Yannick Monnet, Marc Renaudin, Régis Leveugle
2004Automated Logic SER Analysis and On-Line SER reduction.
André K. Nieuwland, Patrick Gindner
2004BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks.
Andrzej Krasniewski
2004Designing a High Speed Decoder for Cyclic Codes.
Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
2004Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection.
Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour
2004Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm.
Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
2004Fault Tolerant Mechatronics.
Elmar Dilger, Roland Karrelmeyer, Bernd Straube
2004Hardware Reconfiguration Scheme for High Availability Systems.
Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni
2004Hybrid Soft Error Detection by Means of Infrastructure IP Cores.
Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
2004Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems.
Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
2004Low Cost On-Line Testing of RF Circuits.
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
2004Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.
José Manuel Cazeaux, Martin Omaña, Cecilia Metra
2004Modeling and Simulation of Time Domain Faults in Digital Systems.
Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2004Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits.
Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Andrej A. Morosov, Michael Gössel
2004New High Speed CMOS Self-Checking Voter.
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2004On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation.
Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
2004On the Design of Long-Life Reliable Systems for Ground-Based Applications.
Jose Miguel Vieira dos Santos
2004On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.
Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2004On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA.
Rodrigo Picos, Miquel Roca, Eugeni Isern, Sebastià A. Bota, Eugenio García
2004Operating System Function Reuse to Achieve Low-Cost Fault Tolerance.
Michele Portolan, Régis Leveugle
2004Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits.
Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
2004Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique.
Bogdan Nicolescu, Yvon Savaria, Raoul Velazco
2004Scan Design and Secure Chip.
David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
2004Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair.
Miguel Garvie, Adrian Thompson
2004Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.
Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel
2004Single-Output Embedded Checkers for Systematic Unordered Codes.
Steffen Tarnick
2004Sizing CMOS Circuits for Increased Transient Error Tolerance.
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2004Survey of the Algorithms in the Column-Matching BIST Method.
Petr Fiser, Hana Kubátová
2004Testing of Hard Faults in Simultaneous Multithreaded Processors.
Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
2004Transient Fault Emulation of Hardened Circuits in FPGA Platforms.
Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena