ICCD C

111 papers

YearTitle / Authors
20172017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017
2017A Common Backend for Hardware Acceleration on FPGA.
Emanuele Del Sozzo, Riyadh Baghdadi, Saman P. Amarasinghe, Marco D. Santambrogio
2017A Cost-Efficient NVM-Based Journaling Scheme for File Systems.
Xiaoyi Zhang, Dan Feng, Yu Hua, Jianxi Chen
2017A Design-for-Test Solution for Monolithic 3D Integrated Circuits.
Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty
2017A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing.
Chi Lo, Yu-Yi Su, Chun-Yi Lee, Shih-Chieh Chang
2017A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function Evaluation.
Jing Chen, Xue Liu
2017A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.
Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang
2017A Scale-Out Enterprise Storage Architecture.
Wonil Choi, Myoungsoo Jung, Mahmut T. Kandemir, Chita R. Das
2017A Shingle-Aware Persistent Cache Management Scheme for DM-SMR Disks.
Tianming Yang, Haitao Wu, Ping Huang, Fei Zhang
2017ABDTR: Approximation-Based Dynamic Traffic Regulation for Networks-on-Chip Systems.
Ling Wang, Xiaohang Wang, Yadong Wang
2017Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks.
Joonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi
2017Adaptive Prefetching for Accelerating Read and Write in NVM-Based File Systems.
Shengan Zheng, Hong Mei, Linpeng Huang, Yanyan Shen, Yanmin Zhu
2017An FPGA-Based Coprocessor for Hash Unit Acceleration.
Abbas A. Fairouz, Sunil P. Khatri
2017Applications of Deep Neural Networks for Ultra Low Power IoT.
Sreela Kodali, Patrick Hansen, Niamh Mulholland, Paul N. Whatmough, David M. Brooks, Gu-Yeon Wei
2017Approximate Disjoint Bi-Decomposition and Its Application to Approximate Logic Synthesis.
Yue Yao, Shuyang Huang, Chen Wang, Yi Wu, Weikang Qian
2017Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads.
Siyuan Xu, Benjamin Carrión Schäfer
2017Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction.
Farimah Farahmandi, Prabhat Mishra
2017Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata.
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2017Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.
Chenguang Wang, Yici Cai, Qiang Zhou
2017BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads.
Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout
2017BioChipWork: Reverse Engineering of Microfluidic Biochips.
Huili Chen, Seetal Potluri, Farinaz Koushanfar
2017CAGE: A Contention-Aware Game-Theoretic Model for Heterogeneous Resource Assignment.
Diman Zad Tootaghaj, Farshid Farhat
2017CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds.
Tianwei Zhang, Yuan Xu, Yungang Bao, Ruby B. Lee
2017Compiler-Assisted Threshold Implementation against Power Analysis Attacks.
Pei Luo, Konstantinos Athanasiou, Liwei Zhang, Zhen Hang Jiang, Yunsi Fei, A. Adam Ding, Thomas Wahl
2017Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration.
Siyuan Xu, Benjamin Carrión Schäfer, Yidi Liu
2017Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory Machines.
Peitian Pan, Chao Li
2017Convolutional Neural Networks on Dataflow Engines.
Nils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk
2017CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash.
Meng Zhang, Fei Wu, Yajuan Du, Chengmo Yang, Changsheng Xie, Jiguang Wan
2017Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra
2017Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk Faults.
Kimia Soleimani, Ahmad Patooghy, Nasim Soltani, Lake Bu, Michel A. Kinsy
2017DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching.
Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh
2017DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems.
Mourad Dridi, Stéphane Rubini, Mounir Lallali, Martha Johanna Sepúlveda Flórez, Frank Singhoff, Jean-Philippe Diguet
2017DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory.
Chengning Wang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Yang Zhang
2017DLL-Assisted Clock Synchronization Method for Multi-Die ICs.
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2017DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.
Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
2017Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores.
Lei Mo, Angeliki Kritikakou, Olivier Sentieys
2017Dependency-Aware Parallel Routing for Large-Scale FPGAs.
Minghua Shen, Nong Xiao, Guojie Luo
2017Design Exploration for Multiple Level Cell Based Non-Volatile FPGAs.
Ke Liu, Mengying Zhao, Lei Ju, Zhiping Jia, Chun Jason Xue, Jingtong Hu
2017Dual Dictionary Compression for the Last Level Cache.
Akshay Lahiry, David R. Kaeli
2017Effective Optimization of Branch Predictors through Lightweight Simulation.
Chaobing Zhou, Libo Huang, Tan Zhang, Yongwen Wang, Chengyi Zhang, Qiang Dou
2017Effective Signal Restoration in Post-Silicon Validation.
Xiaobang Liu, Ranga Vemuri
2017Efficient Tagged Memory.
Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos
2017Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAM.
Jie Xu, Dan Feng, Wei Tong, Jingning Liu, Wen Zhou
2017Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Deliang Fan, Shaahin Angizi
2017Energy-Aware Task Scheduling on Heterogeneous NoC-Based MPSoCs.
Suhaimi Abd Ishak, Hui Wu, Umair Ullah Tariq
2017Estimating the Limits of CPU Power Management for Mobile Games.
Benedikt Dietrich, Nadja Peters, Sangyoung Park, Samarjit Chakraborty
2017Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.
Qiao Li, Liang Shi, Yejia Di, Yajuan Du, Chun Jason Xue, Edwin Hsing-Mean Sha
2017Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Zhezhi He, Shaahin Angizi, Deliang Fan
2017Exploring Scalable Data Allocation and Parallel Computing on NoC-Based Embedded Many Cores.
Yuya Maruyama, Shinpei Kato, Takuya Azumi
2017FSM Anomaly Detection Using Formal Analysis.
Farimah Farahmandi, Prabhat Mishra
2017Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance.
Sonal Pinto, Michael S. Hsiao
2017Fast, Ring-Based Design of 3D Stacked DRAM.
Andrew J. Douglass, Sunil P. Khatri
2017Fingerprinting Field Programmable Gate Arrays.
Vinayaka Jyothi, Ashik Poojari, Richard Stern, Ramesh Karri
2017Floating Point Square Root under HUB Format.
Julio Villalba-Moreno, Javier Hormigo
2017GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms.
Hamza Omar, Masab Ahmad, Omer Khan
2017H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.
Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
2017Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators.
Ruizhe Cai, Ao Ren, Luhao Wang, Massoud Pedram, Yanzhi Wang
2017ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning.
Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng
2017Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks.
Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri
2017Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks.
Ahmed Waheed Khan, Tanya Wanchoo, Gokhan Mumcu, Selçuk Köse
2017Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing.
Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2017Improving Performance of TLC RRAM with Compression-Ratio-Aware Data Encoding.
Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li, Wen Zhou
2017Jenga: Efficient Fault Tolerance for Stacked DRAM.
Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin
2017LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs.
Samuel Steffl, Sherief Reda
2017LDPC-Based Adaptive Multi-Error Correction for 3D Memories.
Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana
2017Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells.
Abhishek Das, Nur A. Touba
2017Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs.
Qutaiba Alasad, Jiann-Shiun Yuan
2017Low Latency Approximate Adder for Highly Correlated Input Streams.
Xiaoliang Chen, Ahmed M. Eltawil, Fadi J. Kurdahi
2017Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network.
Nick Iliev, Amit Ranjan Trivedi
2017Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor.
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
2017M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU Systems.
Christopher E. Giles, Mark A. Heinrich
2017Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures.
Hossein Sayadi, Nisarg Patel, Avesta Sasan, Houman Homayoun
2017Memory-Bounded Randomness for Hardware-Constrained Encrypted Computation.
Nektarios Georgios Tsoutsos, Oleg Mazonka, Michail Maniatakos
2017Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip.
Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
2017NUPLet: A Photonic Based Multi-Chip NUCA Architecture.
Janibul Bashir, Smruti R. Sarangi
2017Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function.
Bingzhe Li, Yaobin Qin, Bo Yuan, David J. Lilja
2017Neural Trojans.
Yuntao Liu, Yang Xie, Ankur Srivastava
2017Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.
Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2017Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.
Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang
2017Power and Area Efficient Sorting Networks Using Unary Processing.
M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
2017Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips.
Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Kevin Skadron, Mircea R. Stan
2017Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao
2017Pulse Ring Oscillator Tuning via Pulse Dynamics.
Aditya Dalakoti, Merritt Miller, Forrest Brewer
2017QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models.
Alif Ahmed, Prabhat Mishra
2017Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Mobile 3D Graphics Applications.
Navid Farazmand, David R. Kaeli
2017Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes.
Mingzhe Zhang, Lunkai Zhang, Lei Jiang, Frederic T. Chong, Zhiyong Liu
2017RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance.
Armin Haj Aboutalebi, Lide Duan
2017RCTP: Region Correlated Temporal Prefetcher.
Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam
2017ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis.
Atieh Lotfi, Rajesh K. Gupta
2017Read Error Resilient MLC STT-MRAM Based Last Level Cache.
Wen Wen, Youtao Zhang, Jun Yang
2017Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic.
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
2017Security Trade-Offs in Microfluidic Routing Fabrics.
Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri
2017SelSMaP: A Selective Stride Masking Prefetching Scheme.
Jiajun Wang, Reena Panda, Lizy Kurian John
2017Sharing-Aware Efficient Private Caching in Many-Core Server Processors.
Sudhanshu Shukla, Mainak Chaudhuri
2017Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.
Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, Swaroop Ghosh
2017Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Yong Shim, Akhilesh Jaiswal, Kaushik Roy
2017Subcomponent Timing-Based Detection of Malware in Embedded Systems.
Sixing Lu, Roman Lysecky, Jerzy W. Rozenblit
2017T2: A Highly Accurate and Energy Efficient Stride Prefetcher.
Sushant Kondguli, Michael C. Huang
2017TAINT: Tool for Automated INsertion of Trojans.
Vinayaka Jyothi, Prashanth Krishnamurthy, Farshad Khorrami, Ramesh Karri
2017TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective.
Tianyue Lu, Yuhang Liu, Haiyang Pan, Mingyu Chen
2017Template Attack Based Deobfuscation of Integrated Circuits.
Abhishek Chakraborty, Yang Xie, Ankur Srivastava
2017The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems.
Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio
2017Timing-Abstract Circuit Design in Transaction-Level Verilog.
Steven F. Hoover
2017Towards Accelerating Generic Machine Learning Prediction Pipelines.
Alberto Scolari, Yunseong Lee, Markus Weimer, Matteo Interlandi
2017Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching.
Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi
2017Using Application-Level Thread Progress Information to Manage Power and Performance.
Sabrina M. Neuman, Jason E. Miller, Daniel Sánchez, Srinivas Devadas
2017Using Disturbance Compensation and Data Clustering (DC)2 to Improve Reliability and Performance of 3D MLC Flash Memory.
Yazhi Feng, Dan Feng, Wei Tong, Yu Jiang, Chuanqi Liu
2017Very Low Voltage (VLV) Design.
Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler
2017Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems.
Yuanwen Huang, Prabhat Mishra
2017Yoda: Judge Me by My Size, Do You?
Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones