ICCD C

81 papers

YearTitle / Authors
201432nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014
20143D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time.
Ishan G. Thakkar, Sudeep Pasricha
2014A Thread-Aware Adaptive Data Prefetcher.
Jiyang Yu, Peng Liu
2014A lightweight and open-source framework for the lifetime estimation of multicore systems.
Cristiana Bolchini, Matteo Carminati, Marco Gribaudo, Antonio Miele
2014A low-power accuracy-configurable floating point multiplier.
Hang Zhang, Wei Zhang, John C. Lach
2014Accelerating divergent applications on SIMD architectures using neural networks.
Beayna Grigorian, Glenn Reinman
2014Accurate prediction of detailed routing congestion using supervised data learning.
Zhongdong Qi, Yici Cai, Qiang Zhou
2014Advanced modes in AES: Are they safe from power analysis based side channel attacks?
Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
2014An area-efficient Ternary CAM design using floating gate transistors.
Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri
2014An asynchronous Network-on-Chip router with low standby power.
Amr Elshennawy, Sunil P. Khatri
2014An energy efficient column-major backend for FPGA SpMV accelerators.
Yaman Umuroglu, Magnus Jahre
2014An optimized diagnostic procedure for pre-bond TSV defects.
Bei Zhang, Vishwani D. Agrawal
2014Analyzing and controlling accuracy in stochastic circuits.
Te-Hsuan Chen, John P. Hayes
2014Automated generation of battery aging models from datasheets.
Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino
2014BarTLB: Barren page resistant TLB for managed runtime languages.
Xin Tong, Andreas Moshovos
2014Boolean circuit design using emerging tunneling devices.
Behnam Sedighi, Joseph J. Nahas, Michael T. Niemier, Xiaobo Sharon Hu
2014Built-in self-test for interposer-based 2.5D ICs.
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
2014Cache design for mixed criticality real-time systems.
N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2014Chip clustering with mutual information on multiple clock tests and its application to yield tuning.
Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou
2014Compact and accurate stochastic circuits with shared random number sources.
Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue
2014CoolBudget: Data center power budgeting with workload and cooling asymmetry awareness.
Ozan Tuncer, Kalyan Vaidyanathan, Kenny C. Gross, Ayse K. Coskun
2014DFM is dead - Long live DFM.
Robert C. Aitken, David Pietromonaco, Brian Cline
2014Dark silicon aware power management for manycore systems under dynamic workloads.
Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Awet Yemane Weldezion, Pasi Liljeberg, Juha Plosila, Axel Jantsch, Hannu Tenhunen
2014Design space exploration of an NVM-based memory hierarchy.
Seungjae Baek, Daeyeon Son, Dongwoo Kang, Jongmoo Choi, Sangyeun Cho
2014Design space exploration of multiple loops on FPGAs using high level synthesis.
Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, Smaïl Niar
2014Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores.
Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg
2014Dynamic associative caches: Reducing dynamic energy of first level caches.
Karthikeyan Dayalan, Meltem Ozsoy, Dmitry V. Ponomarev
2014Dynamic front-end sharing in graphics processing units.
Tao Zhang, Xiaoyao Liang
2014Dynamic variability management in mobile multicore processors under lifetime constraints.
Pietro Mercati, Francesco Paterna, Andrea Bartolini, Luca Benini, Tajana Simunic Rosing
2014Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA.
Levent Aksoy, Paulo F. Flores, José Monteiro
2014Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.
Ryota Shioya, Hideki Ando
2014Equivalence verification for NULL Convention Logic (NCL) circuits.
Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith
2014Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems.
Congming Gao, Liang Shi, Kaijie Wu, Chun Jason Xue, Edwin Hsing-Mean Sha
2014Exploiting natural redundancy in visual information.
Chris S. Lee, Kevin M. Irick, Jack Sampson, Chuanjun Zhang, Vijaykrishnan Narayanan
2014Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
2014Fair share: Allocation of GPU resources for both performance and fairness.
Paula Aguilera, Katherine Morrow, Nam Sung Kim
2014HAP: Hybrid-memory-Aware Partition in shared Last-Level Cache.
Wei Wei, Dejun Jiang, Jin Xiong, Mingyu Chen
2014HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs.
Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk
2014Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips.
Costas Iordanou, Vassos Soteriou, Konstantinos Aisopos
2014Hybrid modeling attacks on current-based PUFs.
Raghavan Kumar, Wayne P. Burleson
2014ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap.
Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath
2014Improved signoff methodology with tightened BEOL corners.
Tuck-Boon Chan, Sorin Dobre, Andrew B. Kahng
2014Improving multilevel PCM reliability through age-aware reading and writing strategies.
Chen Liu, Chengmo Yang
2014Improving power delivery network design by practical methodologies.
Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai
2014Increasing cache capacity via critical-words-only cache.
Cheng-Chieh Huang, Vijay Nagarajan
2014Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.
Daming Zhang, Shuangchen Li, Ang Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang
2014Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory.
Mengying Zhao, Liang Shi, Chengmo Yang, Chun Jason Xue
2014Leveraging dynamic slicing to enhance indirect branch prediction.
Walid J. Ghandour, Nadine J. Ghandour
2014Loose-Ordering Consistency for persistent memory.
Youyou Lu, Jiwu Shu, Long Sun, Onur Mutlu
2014Low write-energy STT-MRAMs using FinFET-based access transistors.
Alireza Shafaei, Yanzhi Wang, Massoud Pedram
2014Modeling and analysis of Phase Change Materials for efficient thermal management.
Fulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne P. Burleson, Dean M. Tullsen, Ayse K. Coskun
2014More Moore landscape for system readiness - ITRS2.0 requirements.
Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, Sunggeun Kim, Gerhard Klimeck, Chorng-Ping Chang, Charles Cheung, Yuzo Fukuzaki
2014Multi-accelerator system development with the ShrinkFit acceleration framework.
Michael J. Lyons, Gu-Yeon Wei, David M. Brooks
2014NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores.
Xiang Pan, Radu Teodorescu
2014Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs.
Stelios N. Neophytou, Maria K. Michael
2014Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.
Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li
2014PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs.
Nishit Ashok Kapadia, Sudeep Pasricha
2014Pattern-restricted design at 10nm and beyond.
Rani S. Ghaida, Yasmine Badr, Puneet Gupta
2014Power supply and consumption co-optimization of portable embedded systems with hybrid power supply.
Xue Lin, Yanzhi Wang, Naehyuck Chang, Massoud Pedram
2014Power-capped DVFS and thread allocation with ANN models on modern NUMA systems.
Satoshi Imamura, Hiroshi Sasaki, Koji Inoue, Dimitrios S. Nikolopoulos
2014ProactiveDRAM: A DRAM-initiated retention management scheme.
Jue Wang, Xiangyu Dong, Yuan Xie
2014QoS management on heterogeneous architecture for parallel applications.
Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng
2014REEM: Failure/non-failure region estimation method for SRAM yield analysis.
Manish Rana, Ramon Canal
2014ReMAP: Reuse and memory access cost aware eviction policy for last level cache management.
Akhil Arunkumar, Carole-Jean Wu
2014Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.
Siddharth Advani, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin M. Irick, Yong Cheol Peter Cho, Jack Sampson, Vijaykrishnan Narayanan
2014SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache.
Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam
2014ScalaHDL: Express and test hardware designs in a Scala DSL.
Yao Li, Antonio Roldao Lopes, Zhouyun Xu, Zhengwei Qi, Haibing Guan
2014Simultaneous EUV flare- and CMP-aware placement.
Chi-Yuan Liu, Yao-Wen Chang
2014Software pipelining of dataflow programs with dynamic constructs on multi-core processor.
Yogesh Murarka, Pankaj Shailendra Gode, Sirish Kumar Pasupuleti, Soma Kohli
2014Static thread mapping for NoCs via binary instrumentation traces.
Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More
2014Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.
Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar
2014Ternary cache: Three-valued MLC STT-RAM caches.
Seokin Hong, Jongmin Lee, Soontae Kim
2014The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost.
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu
2014The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap.
Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto
2014The heterogeneous block architecture.
Chris Fallin, Chris Wilkerson, Onur Mutlu
2014Timing characterization of clock buffers for clock tree synthesis.
Can Sitik, Scott Lerner, Baris Taskin
2014Timing error masking by exploiting operand value locality in SIMD architecture.
Jaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim
2014Updates of the ITRS design cost and power models.
Gary Smith
2014Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology.
Qing Xie, Yanzhi Wang, Shuang Chen, Massoud Pedram
2014Write-aware random page initialization for non-volatile memory systems.
Fei Xia, Dejun Jiang, Jin Xiong, Ninghui Sun
2014iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.
Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio