ICCD C

84 papers

YearTitle / Authors
201028th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings
2010A co-processor approach for accelerating data-structure intensive algorithms.
Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden
2010A control-theoretic energy management for fault-tolerant hard real-time systems.
Ali Sharif Ahmadian, Mahdieh Hosseingholi, Alireza Ejlali
2010A fine-grained link-level fault-tolerant mechanism for networks-on-chip.
Arseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos
2010A flexible simulation methodology and tool for nanoarray-based architectures.
Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
2010A high performance router with dynamic buffer allocation for on-chip interconnect networks.
Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li
2010A lightweight run-time scheduler for multitasking multicore stream applications.
Michael A. Baker, Karam S. Chatha
2010A radix-10 digit recurrence division unit with a constant digit selection function.
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010A simple pipelined logarithmic multiplier.
Patricio Bulic, Zdenka Babic, Aleksej Avramovic
2010A study on performance benefits of core morphing in an asymmetric multicore processor.
Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu
2010A tag-based cache replacement.
Chuanjun Zhang, Bing Xue
2010A unified addition structure for moduli set {2
Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana
2010A voting-based working set assessment scheme for dynamic cache resizing mechanisms.
Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
2010Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems.
Paolo Burgio, Martino Ruggiero, Francesco Esposito, Mauro Marinoni, Giorgio C. Buttazzo, Luca Benini
2010An energy model for graphics processing units.
Jeff Pool, Anselmo Lastra, Montek Singh
2010Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matching.
Felix Eberli
2010BDD-based circuit restructuring for reducing dynamic power.
Quang Dinh, Deming Chen, Martin D. F. Wong
2010Bandwidth optimization in asynchronous NoCs by customizing link wire length.
JunBok You, Daniel Gebhardt, Kenneth S. Stevens
2010Boolean factoring with multi-objective goals.
Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis
2010Combined optimal and heuristic approaches for multiple constant multiplication.
Jason Thong, Nicola Nicolici
2010Computational models for the age of multicore processing.
Wolfgang J. Paul
2010Countering code injection attacks with TLB and I/O monitoring.
Dongkyun Ahn, Gyungho Lee
2010Crosstalk modeling to predict channel delay in Network-on-Chips.
Ahmad Patooghy, Seyed Ghassem Miremadi, Mansour Shafaei
2010DDPSL: An easy way of defining properties.
Luigi Di Guglielmo, Franco Fummi, Nicola Orlandi, Graziano Pravadelli
2010DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time.
Wei Shi, Zhiying Wang, Hongguang Ren, Ting Cao, Wei Chen, Bo Su, Hongyi Lu
2010Data rate maximization by adaptive thresholding RF power management under renewable energy.
Weiguo Tang, Lei Wang
2010Delay test quality maximization through process-aware selection of test set size.
Baris Arslan, Alex Orailoglu
2010Design and implementation of a special purpose embedded system for neural machine interface.
Xiaorong Zhang, He Huang, Qing Yang
2010DfT optimization for pre-bond testing of 3D-SICs containing TSVs.
Jia Li, Dong Xiang
2010Dynamic register file partitioning in superscalar microprocessors for energy efficiency.
Meltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp, Oguz Ergin
2010EQUIPE: Parallel equivalence checking with GP-GPUs.
Debapriya Chatterjee, Valeria Bertacco
2010Efficient MIMD architectures for high-performance ray tracing.
Daniel M. Kopta, Josef B. Spjut, Erik Brunvand, Al Davis
2010Efficient provably good OPC modeling and its applications to interconnect optimization.
Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang
2010Efficient test response compaction for robust BIST using parity sequences.
Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand
2010Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators.
Zhuo Ruan, Kurtis Cahill, David A. Penry
2010Energy optimal on-line Self-Test of microprocessors in WSN nodes.
Andreas Merentitis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis
2010Enhancing dual-Vt design with consideration of on-chip temperature variation.
Junjun Gu, Gang Qu, Lin Yuan
2010Exploiting SIMD extensions for linear image processing with OpenCL.
Samuel Antao, Leonel Sousa
2010Exploiting application-dependent ambient temperature for accurate architectural simulation.
Hyung Beom Jang, Jinhang Choi, Ikroh Yoon, Sung-Soo Lim, Seungwon Shin, Naehyuck Chang, Sung Woo Chung
2010Feasibility study of dynamic Trusted Platform Module.
Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri
2010Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.
Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita
2010Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors.
Ali Shafiee, Narges Shahidi, Amirali Baniasadi
2010High throughput, low set-up time, reconfigurable linear Feedback Shift Registers.
Rick J. M. Nas, C. H. van Berkel
2010IP characterization methodology for fast and accurate power consumption estimation at transactional level model.
Michel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois
2010Identifying optimal generic processors for biomedical implants.
Christos Strydis, Dhara Dave
2010Implicit hints: Embedding hint bits in programs without ISA changes.
Hans Vandierendonck, Koen De Bosschere
2010Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms.
Rami Sheikh, Mazen Kharbutli
2010Incremental gate sizing for late process changes.
John Lee, Puneet Gupta
2010Insertion policy selection using Decision Tree Analysis.
Samira Manabi Khan, Daniel A. Jiménez
2010Inter-socket victim cacheing for platform power reduction.
Subhra Mazumdar, Dean M. Tullsen, Justin J. Song
2010LMS-based low-complexity game workload prediction for DVFS.
Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty, Matthias Gries
2010Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU.
Seokin Hong, Soontae Kim
2010Lowering the latency of interfaces for rationally-related frequencies.
Jean-Michel Chabloz, Ahmed Hemani
2010M5 based EDGE architecture modeling.
Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang
2010Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization.
Sanghamitra Roy, Koushik Chakraborty
2010Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC.
Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim
2010On mismatch number distribution of nanocrossbar logic mapping.
Yehua Su, Wenjing Rao
2010Optimal power/performance pipelining for error resilient processors.
Nicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar
2010Optimization of back pressure and throughput for latency insensitive systems.
Bin Xue, Sandeep K. Shukla
2010Out-of-order retirement of instructions in sequentially consistent multiprocessors.
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, David R. Kaeli
2010Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCs.
Shervin Sharifi, Tajana Simunic Rosing
2010Practical completion detection for 2-of-N delay-insensitive codes.
Marco Cannizzaro, Weiwei Jiang, Steven M. Nowick
2010Predicting the throughput of multiprocessor applications under dynamic workload.
Peter Poplavko, Marc Geilen, Twan Basten
2010Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms.
Shohreh Sharif Mansouri, Elena Dubrova
2010QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin.
Yue Qian, Zhonghai Lu, Qiang Dou
2010RTOS-aware modeling of embedded hardware/software systems.
Matthias Müller, Joachim Gerlach, Wolfgang Rosenstiel
2010Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systems.
Linwei Niu
2010Recent additions to the ARMv7-A architecture.
David Brash
2010Robust and energy-efficient DSP systems via output probability processing.
Rami A. Abdallah, Naresh R. Shanbhag
2010Routability-driven flip-flop merging process for clock power reduction.
Zhi-Wei Chen, Jin-Tai Yan
2010SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS.
Tushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang
2010Scenario-based design space exploration of MPSoCs.
Peter van Stralen, Andy D. Pimentel
2010Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array.
Vinayak Honkote, Baris Taskin
2010Spintronic logic gates for spintronic data using magnetic tunnel junctions.
Shruti Patil, Andrew Lyle, Jonathan D. Harms, David J. Lilja, Jianping Wang
2010Sub-threshold charge recovery circuits.
Mehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali
2010Temperature-to-power mapping.
Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan
2010The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis
2010Thermal-aware scratchpad memory design and allocation.
Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal
2010Threads vs. caches: Modeling the behavior of parallel workloads.
Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2010Toward reliable SRAM-based device identification.
Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham
2010Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability.
Yu Liu, Kaijie Wu
2010Using variable clocking to reduce leakage in synchronous circuits.
Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
2010VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.
Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2010Welcome to ICCD 2010!
Peter-Michael Seidel, Georgi Gaydadjiev, Sofiène Tahar, Lars J. Svensson